Abstract
This paper analyses two methods of organizing parallelism for the Smith-Waterman algorithm, and show how they perform relative to peak performance when the amount of parallelism varies. A novel systolic design is introduced, with a processing element optimized for computing the affine gap cost function. Our FPGA design is significantly more energy-efficient than GPU designs. For example, our design for the XC5VLX330T FPGA achieves around 16 GCUPS/W, while CPUs and GPUs have a power efficiency of lower than 0.5 GCUPS/W.
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Yamaguchi, Y., Tsoi, H.K., Luk, W. (2011). FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design. In: Koch, A., Krishnamurthy, R., McAllister, J., Woods, R., El-Ghazawi, T. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2011. Lecture Notes in Computer Science, vol 6578. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19475-7_20
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DOI: https://doi.org/10.1007/978-3-642-19475-7_20
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-19474-0
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