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Reasoning about the Implementation of Concurrency Abstractions on x86-TSO

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ECOOP 2010 – Object-Oriented Programming (ECOOP 2010)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 6183))

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Abstract

With the rise of multi-core processors, shared-memory concurrency has become a widespread feature of computation, from hardware, to operating systems, to programming languages such as C++ and Java. However, none of these provide sequentially consistent shared memory; instead they have relaxed memory models, which make concurrent programs even more challenging to understand. Programming language implementations run on hardware memory models, so VM and run-time system implementors must reason at both levels. Of particular interest are the low-level implementations of the abstractions that support language-level concurrency—especially because they invariably contain data races.

In this paper, we develop a novel principle for reasoning about assembly programs on our previous x86-TSO memory model, and we use it to analyze five concurrency abstraction implementations: two spinlocks (from Linux); a non-blocking write protocol; the double-checked locking idiom; and java.util.concurrent’s Parker. Our principle, called triangular-race freedom, strengthens the usual data-race freedom style of reasoning.

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References

  1. Adve, S.V., Gharachorloo, K.: Shared memory consistency models: A tutorial. IEEE Computer 29(12), 66–76 (1996)

    Google Scholar 

  2. Adve, S.V., Hill, M.D.: A unified formalization of four shared-memory models. IEEE Trans. Parallel Distrib. Syst. 4(6), 613–624 (1993)

    Article  Google Scholar 

  3. Ahamad, M., Neiger, G., Burns, J.E., Kohli, P., Hutto, P.W.: Causal memory: Definitions, implementation, and programming. Distributed Computing 9(1) (1995)

    Google Scholar 

  4. AMD64 Architecture Programmer’s Manual (3 vols). Advanced Micro Devices, rev. 3.14 (September 2007)

    Google Scholar 

  5. Aspinall, D., Ševčík, J.: Formalising Java’s data race free guarantee. In: Schneider, K., Brandt, J. (eds.) TPHOLs 2007. LNCS, vol. 4732, pp. 22–37. Springer, Heidelberg (2007)

    Chapter  Google Scholar 

  6. Boehm, H.-J., Adve, S.V.: Foundations of the C++ concurrency memory model. In: Proc. Prog. Language Design and Implementation, pp. 68–78. ACM, New York (2008)

    Google Scholar 

  7. Boudol, G., Petri, G.: Relaxed memory models: An operational approach. In: Proc. Principles of Programming Languages, pp. 392–403. ACM, New York (2009)

    Google Scholar 

  8. Brookes, S.: A semantics for concurrent separation logic. Theor. Comput. Sci. 375(1-3), 227–270 (2007)

    Article  MATH  MathSciNet  Google Scholar 

  9. Burckhardt, S., Musuvathi, M.: Effective program verification for relaxed memory models. In: Gupta, A., Malik, S. (eds.) CAV 2008. LNCS, vol. 5123, pp. 107–120. Springer, Heidelberg (2008)

    Chapter  Google Scholar 

  10. Cohen, E., Schirmer, N.: A better reduction theorem for store buffers. arXiv:0909.4637v1 (2009)

    Google Scholar 

  11. Dice, D.: Java memory model concerns on Intel and AMD systems (January 2008), http://blogs.sun.com/dave/ (accessed 2009/12/13)

  12. Dice, D.: A race in LockSupport park() arising from weak memory models (November 2009), http://blogs.sun.com/dave/ (accessed 2009/12/13)

  13. The “double-checked locking is broken” declaration, http://www.cs.umd.edu/~pugh/java/memoryModel/DoubleCheckedLocking.html

  14. Friedman, R.: Consistency Conditions for Distributed Shared Memories. PhD thesis, Technion: Israel Institute of Technology (1994)

    Google Scholar 

  15. Intel 64 and IA-32 Architectures Software Developer’s Manual. Intel Corporation, April(vol 1,2A,2B; rev.27), Februay(vol.3A,3B; rev.26) (2008)

    Google Scholar 

  16. ISO/IEC 14882, programming languages - C++. WG21 n2800 (October 2008)

    Google Scholar 

  17. Jones, C.B.: Accommodating interference in the formal design of concurrent object-based programs. Form. Methods Syst. Des. 8(2), 105–122 (1996)

    Article  Google Scholar 

  18. JSR 133: Java memory model and thread specification revision, http://jcp.org/en/jsr/detail?id=133

  19. Kopetz, H., Reisinger, J.: The non-blocking write protocol NBW: A solution to a real-time synchronisation problem. In: Real-Time Systems Symposium (1993)

    Google Scholar 

  20. Lameter, C.: Effective synchronization on Linux/NUMA systems. In: Gelato Conference. Silicon Graphics, Inc. (2005), http://www.lameter.com/gelato2005.pdf

  21. Lamport, L.: How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Trans. Computers 28(9), 690–691 (1979)

    Article  MATH  Google Scholar 

  22. Linux kernel mailing list (November 1999), Subj.: spin_unlock optimization(i386)

    Google Scholar 

  23. Luchango, V.: Memory Consistency Models for High Performance Distributed Computing. PhD thesis, Massachusetts Institute of Technology (2001)

    Google Scholar 

  24. Meyers, S., Alexandrescu, A.: C++ and the perils of double-checked locking. Dr. Dobbs Journal (July-August 2004)

    Google Scholar 

  25. Norrish, M., Slind, K.: Hol-4, http://hol.sourceforge.net/

  26. O’Hearn, P.W.: Resources, concurrency, and local reasoning. Theor. Comput. Sci. 375(1-3), 271–307 (2007)

    Article  MATH  MathSciNet  Google Scholar 

  27. Owens, S., Sarkar, S., Sewell, P.: A better x86 memory model: x86-TSO. In: Urban, C. (ed.) TPHOLs 2009. LNCS, vol. 5674, pp. 391–407. Springer, Heidelberg (2009)

    Google Scholar 

  28. Park, S., Dill, D.L.: An executable specification and verifier for relaxed memory order. IEEE Trans. Computers 48(2), 227–235 (1999)

    Article  Google Scholar 

  29. Pugh, W.: The Java memory model is fatally flawed. Concurrency - Practice and Experience 12(6), 445–455 (2000)

    Article  Google Scholar 

  30. Saraswat, V.A., Jagadeesan, R., Michael, M.M., von Praun, C.: A theory of memory models. In: Principles and Practice of Parallel Programming (2007)

    Google Scholar 

  31. Sarkar, S., Sewell, P., Zappa Nardelli, F., Owens, S., Ridge, T., Braibant, T., Myreen, M.O., Alglave, J.: The semantics of x86-CC multiprocessor machine code. In: Proc. Principles of Programming Languages, pp. 379–391. ACM, New York (2009)

    Google Scholar 

  32. Schmidt, D.C., Harrison, T.: Double-checked locking. In: Pattern Languages of Program Design 3. Addison-Wesley, Reading (1997)

    Google Scholar 

  33. Shasha, D., Snir, M.: Efficient and correct execution of parallel programs that share memory. ACM Trans. Program. Lang. Syst. 10(2), 282–312 (1988)

    Article  Google Scholar 

  34. SPARC International, Inc. The SPARC Architecture Manual: Version 8. Prentice Hall, Englewood Cliffs (1992)

    Google Scholar 

  35. Ševčík, J., Aspinall, D.: On validity of program transformations in the Java memory model. In: Vitek, J. (ed.) ECOOP 2008. LNCS, vol. 5142, pp. 27–51. Springer, Heidelberg (2008)

    Google Scholar 

  36. Visser, W., Havelund, K., Brat, G.P., Park, S., Lerda, F.: Model checking programs. Autom. Softw. Eng. 10(2), 203–232 (2003)

    Article  Google Scholar 

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Authors and Affiliations

  1. University of Cambridge,  

    Scott Owens

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  1. Scott Owens
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Editors and Affiliations

  1. Software Languages Lab, Vrije Universiteit Brussel, Pleinlaan 2, 1050, Brussels, Belgium

    Theo D’Hondt

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Owens, S. (2010). Reasoning about the Implementation of Concurrency Abstractions on x86-TSO. In: D’Hondt, T. (eds) ECOOP 2010 – Object-Oriented Programming. ECOOP 2010. Lecture Notes in Computer Science, vol 6183. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-14107-2_23

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  • DOI: https://doi.org/10.1007/978-3-642-14107-2_23

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-14106-5

  • Online ISBN: 978-3-642-14107-2

  • eBook Packages: Computer ScienceComputer Science (R0)

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