Abstract
Whilst clock fault attacks are known to be a serious security threat, an in-depth explanation of such faults still seems to be put in order.
This work provides a theoretical analysis, backed by practical experiments, explaining when and how clock faults occur. Understanding and modeling the chain of events following a transient clock alteration allows to accurately predict faulty circuit behavior. A prediction fully confirmed by injecting variable-duration faults at predetermined clock cycles.
We illustrate the process by successfully attacking an fpga aes implementation using a dll-based fpga platform (one-bit fault attack).
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Agoyan, M., Dutertre, JM., Naccache, D., Robisson, B., Tria, A. (2010). When Clocks Fail: On Critical Paths and Clock Faults. In: Gollmann, D., Lanet, JL., Iguchi-Cartigny, J. (eds) Smart Card Research and Advanced Application. CARDIS 2010. Lecture Notes in Computer Science, vol 6035. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12510-2_13
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DOI: https://doi.org/10.1007/978-3-642-12510-2_13
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