Abstract
Electro Static Discharge (ESD) analysis is of vital importance during the design of large-scale integrated circuits, since it gives insight in how well the interconnect can handle unintended peak charges. Due to the increasing amount of interconnect and metal layers, ESD analysis may become very time consuming or even unfeasible. We propose an algorithm for the reduction of large resistor networks, that typically arise during ESD, to much smaller equivalent networks. Experiments show reduction and speed-ups up to a factor 10.
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Rommes, J., Lenaers, P., Schilders, W.H.A. (2010). Reduction of Large Resistor Networks. In: Roos, J., Costa, L. (eds) Scientific Computing in Electrical Engineering SCEE 2008. Mathematics in Industry(), vol 14. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12294-1_68
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DOI: https://doi.org/10.1007/978-3-642-12294-1_68
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