Abstract
We present a framework to graphically describe and analyze embedded systems which are built on asynchronously wired synchronous subsystems. Our syntax is close to electronic diagrams. In particular, it uses logic and arithmetic gates, connected by wires, and models synchronous subsystems as boxes containing these gates.
In our approach, we introduce a continuous-time semantics, connecting each point of the diagram to a value, at any moment. We then describe an analysis derived from the abstract interpretation framework enabling to statically and automatically prove temporal properties of the diagrams we defined. We can prove, for example, that the output of a diagram cannot be equal to a given value in a given interval of time.
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Bertrane, J. (2005). Static Analysis by Abstract Interpretation of the Quasi-synchronous Composition of Synchronous Programs. In: Cousot, R. (eds) Verification, Model Checking, and Abstract Interpretation. VMCAI 2005. Lecture Notes in Computer Science, vol 3385. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30579-8_7
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DOI: https://doi.org/10.1007/978-3-540-30579-8_7
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