On the Phase Coupling Problem Between Data Memory Layout Generation and Address Pointer Assignment

Abstract

Digital signal processors provide dedicated address generation units that support zero-cost address pointer modifications within a limited offset range. In order to fully exploit these features, program variables must be carefully placed in memory. However, the problem of generating optimum data memory layouts is NP-hard. Efficient heuristics are available for offset ranges ± 1 and ± 2. For an arbitrary set of zero-cost address offsets, optimum memory layout generation can be represented as a quadratic assignment problem (QAP) and solved by a heuristic technique such as simulated annealing (SA). A total number of N! layouts exist where N is the number of different program variables. The solution space becomes even larger in case of multiple address pointers. For each coloring of the access sequence, which corresponds to a specific address pointer assignment, an optimum memory layout has to be found by solving a separate QAP. So far no efficient heuristics exist for combining memory layout generation with address pointer assignment. We show that for a fixed layout optimum address pointer assignments can produced for a given maximum number of K address pointers. The complexity of this algorithm is of O(N ^K). It has been applied to the OffsetStone benchmark suite. As can be demonstrated by some examples, memory layout generation and address pointer assignment are strongly interdependent problems. We introduce a new algorithm that iterates over several optimized layout generation and optimum pointer assignments steps. Experimental results indicate that compared to SA this new technique produces results of equal quality in less time.