Abstract
We describe a viable approach for memory abstraction that preserves memory semantics, thereby augmenting the capability of SAT-based BMC to handle designs with large embedded memory without explicitly modeling each memory bit. Our method does not require examining the design or changing the SAT-solver and is guaranteed not to generate false negatives. The proposed method is similar, but with key enhancements, to the previous abstract interpretation of memory that captures its forwarding semantics, i.e., a data read from a memory location is same as the most recent data written at the same location. In our method, we construct an abstract model for BMC by eliminating memory arrays, but retaining the memory interface signals and adding constraints on those signals at every analysis depth to preserve the memory semantics. The size of these memory-modeling constraints depends quadratically on the number of memory accesses and linearly on the bus widths of memory interface signals. Since the analysis depth of BMC bounds the number of memory accesses, these constraints are significantly smaller than the explicit memory model. The novelty of our memory-modeling constraints is that they capture the exclusivity of a read and write pair explicitly, i.e., when a SAT-solver decides on a valid read and write pair, other pairs are implied invalid immediately, thereby reducing the solve time. We have implemented these techniques in our SAT-based BMC framework where we demonstrate the effectiveness of such an abstraction on a number of hardware and software designs with large embedded memories. We show at least an order of magnitude improvement (both in time and space) using our method over explicit modeling of each memory bit. We also show that our method of adding constraints boosts the performance of the SAT solver (in BMC) significantly as opposed to the conventional way of modeling these constraints as nested if-then-else expressions.
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References
Biere, A., Cimatti, E.M., Clarke, M.: Symbolic model checking using SAT procedures instead of BDDs. In: Proceedings of the Design Automation Conference, pp. 317–320 (1999)
Bjesse, P., Claessen, K.: SAT-based verification without state space traversal. In: Proceedings of Conference on Formal Methods in Computer-Aided Design (2000)
Ganai, M., Aziz, A.: Improved SAT-based Bounded Reachability Analysis. In: Proceedings of VLSI Design Conference (2002)
P. A. Abdulla, P. Bjesse, and N. Een, "Symbolic Reachability Analysis based on {SAT}- Solvers," in Proceedings of Workshop on Tools and Algorithms for the Analysis and Construction of Systems (TACAS), 2000.
Clarke, E.M., Grumberg, O., Peled, D.: Model Checking. MIT Press, Cambridge (1999)
McMillan, K.L.: Symbolic Model Checking: An Approach to the State Explosion Problem. Kluwer Academic Publishers, Dordrecht (1993)
Marques-Silva, J.P., Sakallah, K.A.: GRASP: A Search Algorithm for Propositional Satisfiability. IEEE Transactions on Computers 48, 506–521 (1999)
Zhang, H.: SATO: An efficient propositional prover. In: McCune, W. (ed.) CADE 1997. LNCS, vol. 1249, pp. 272–275. Springer, Heidelberg (1997)
Moskewicz, M., Madigan, C., Zhao, Y., Zhang, L., Malik, S.: Chaff: Engineering an Efficient SAT Solver. In: Proceedings of Design Automation Conference (2001)
Ganai, M., Zhang, L., Ashar, P., Gupta, A.: Combining Strengths of Circuit-based and CNF-based Algorithms for a High Performance SAT Solver. In: Proceedings of the Design Automation Conference (2002)
Kuehlmann, A., Ganai, M., Paruthi, V.: Circuit-based Boolean Reasoning. In: Proceedings of Design Automation Conference (2001)
Burch, J.R., Dill, D.L.: Automatic verification of pipelined microprocessor control. In: Dill, D.L. (ed.) CAV 1994. LNCS, vol. 818, pp. 68–80. Springer, Heidelberg (1994)
Long, D.E.: Model checking, abstraction and compositional verification. Carnegie Mellon University (1993)
Kurshan, R.P.: Computer-Aided Verification of Co-ordinating Processes: The Automata- Theoretic Approach. Princeton University Press, Princeton (1994)
Clarke, E.M., Grumberg, O., Jha, S., Lu, Y., Veith, H.: Counterexample-guided abstraction refinement. In: Emerson, E.A., Sistla, A.P. (eds.) CAV 2000. LNCS, vol. 1855, pp. 154–169. Springer, Heidelberg (2000)
Clarke, E.M., Gupta, A., Kukula, J., Strichman, O.: SAT based abstraction-refinement using ILP and machine learning techniques. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol. 2404, p. 265. Springer, Heidelberg (2002)
Wang, D., Ho, P.-H., Long, J., Kukula, J., Zhu, Y., Ma, T., Damiano, R.: Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines. In: 38th Design Automation Conference (2001)
Chauhan, P., Clarke, E.M., Kukula, J., Sapra, S., Veith, H., Wang, D.: Automated Abstraction Refinement for Model Checking Large State Spaces using SAT based Conflict Analysis. In: Proceedings of FMCAD (2002)
McMillan, K., Amla, N.: Automatic Abstraction without Counterexamples. In: Tools and Algorithms for the Construction and Analysis of Systems (April 2003)
Gupta, M., Ganai, P.: Iterative Abstraction using SAT-based BMC with Proof Analysis. In: Proceedings of International Conference on Computer-Aided Design (2003)
Velev, M.N., Bryant, R.E., Jain, A.: Efficient Modeling of Memory Arrays in Symbolic Simulation. In: Grumberg, O. (ed.) Computer Aided Verification, pp. 388–399 (1997)
Bryant, R.E., German, S., Velev, M.N.: Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic. In: Halbwachs, N., Peled, D. (eds.) Computer-Aided Verification, pp. 470–482. Springer, Heidelberg (1999)
Velev, M.N.: Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors. In: Proceedings of Tools and Algorithms for the Construction and Analysis of Systems, pp. 252–267 (2001)
Lahiri, S.K., Seshia, S.A., Bryant, R.E.: Modeling and Verification of Out-of-Order Microprocessors in UCLID. In: Proceedings of Formal Methods in Computer-Aided Design, pp. 142–159 (2002)
Bryant, R.E., Lahiri, S.K., Seshia, S.A.: Modeling and Verifying Systems using a Logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions. In: Computer-Aided Verification (2002)
Biere, A., Cimatti, E.M.: Symbolic Model Checking without BDDs. In: Cleaveland, W.R. (ed.) TACAS 1999. LNCS, vol. 1579, p. 193. Springer, Heidelberg (1999)
Sheeran, M., Singh, S., Stalmarck, G.: Checking Safety Properties using Induction and a SAT Solver. In: Proceedings of Conference on Formal Methods in Computer-Aided Design (2000)
Pilarski, S., Hu, G.: Speeding up SAT for EDA. In: Proceedings of Design Automation and Test in Europe, p. 1081 (2002)
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Ganai, M.K., Gupta, A., Ashar, P. (2004). Efficient Modeling of Embedded Memories in Bounded Model Checking. In: Alur, R., Peled, D.A. (eds) Computer Aided Verification. CAV 2004. Lecture Notes in Computer Science, vol 3114. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-27813-9_34
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DOI: https://doi.org/10.1007/978-3-540-27813-9_34
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