Abstract
This paper investigates the use of Triple Modular Redundancy (TMR) in hardware accelerators designs described in C programming language and synthesized by High Level Synthesis (HLS). A setup composed of a soft-core processor and a matrix multiplication design protected by TMR and embedded into an SRAM-based FPGA was analyzed under accumulated bit-flips in its configuration memory bits. Different configurations using single and multiple input and output workload data streams were tested. Results show that by using a coarse grain TMR with triplicated inputs, voters, and outputs, it is possible to reach 95% of reliability by accumulating up to 61 bit-flips and 99% of reliability by accumulating up to 17 bit-flips in the configuration memory bits. These numbers imply in a Mean Time Between Failure (MTBF) of the coarse grain TMR at ground level from 50% to 70% higher than the MTBF of the unhardened version for the same reliability confidence.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Carmichael, C.: Triple Module Redundancy Design Techniques for Virtex FPGAs. Xilinx, Application Note XAPP197, July 2006
Habinc, S.: Functional Triple Modular Redundancy (FTMR). Gaisler Research, Design and Assessment Report FPGA-003-01, December 2002
Xilinx: Vivado Design Suite - User Guide - High-Level Synthesis. UG902 (v2014.3), 1 October 2014
Tambara, L.A., Kastensmidt, F.L., Rech, P., Frost, C.: Decreasing FIT with diverse triple modular redundancy in SRAM-based FPGAs. In: Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp. 1–6, November 2014
Tonfat, J., Tambara, L., Santos, A., Kastensmidt, F.: Method to analyze the susceptibility of HLS designs in SRAM-based FPGAs under soft errors. In: Bonato, V., Bouganis, C., Gorgon, M. (eds.) ARC 2016. LNCS, vol. 9625, pp. 132–143. Springer, Heidelberg (2016). doi:10.1007/978-3-319-30481-6_11
Winterstein, F., Bayliss, S., Constantinides, G.A.: High-level synthesis of dynamic data structures: a case study using Vivado HLS. In: Proceedings of International Conference on Field-Programmable Technology, pp. 362–365, December 2013
Tambara, L.A., Tonfat, J., Santos, A., Lima Kastensmidt, F., Medina, N.H., Added, N., Aguiar, V.A.P., Aguirre, F., Silveira, M.A.G.: Analyzing reliability and performance trade-offs of HLS-based designs in SRAM-based FPGAs under soft errors. IEEE Trans. Nucl. Sci. 1, 1–8 (2017). ISSN: 0018-9499
Chan, X., Yang, W., Zhao, M., Wang, J.: HLS-based sensitivity-induced soft error mitigation for satellite communication systems. In: 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 143–148 (2016). ISSN 1942-9401
Xilinx: AXI4-Stream Accelerator Adapter v2.1. PG081 18 November 2015
JEDEC: Measurement and Reporting of Alpha Particle and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices JEDEC Standard (2006). http://www.jedec.org/sites/default/files/docs/jesd89a.pdf
Xilinx Inc.: Device Reliability Report, UG116 (v9.4) (2015)
Crowe, D., Feinberg, A.: Design for Reliability (2001). ISBN 13:978-1-4200-4084-5. https://www.crcpress.com/
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer International Publishing AG
About this paper
Cite this paper
dos Santos, A.F., Tambara, L.A., Benevenuti, F., Tonfat, J., Kastensmidt, F.L. (2017). Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs. In: Wong, S., Beck, A., Bertels, K., Carro, L. (eds) Applied Reconfigurable Computing. ARC 2017. Lecture Notes in Computer Science(), vol 10216. Springer, Cham. https://doi.org/10.1007/978-3-319-56258-2_18
Download citation
DOI: https://doi.org/10.1007/978-3-319-56258-2_18
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-56257-5
Online ISBN: 978-3-319-56258-2
eBook Packages: Computer ScienceComputer Science (R0)