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Efficient Deadlock-Freedom Checking Using Local Analysis and SAT Solving

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Integrated Formal Methods (IFM 2016)

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Abstract

We build upon established techniques of deadlock analysis by formulating a new sound but incomplete framework for deadlock freedom analysis that tackles some sources of imprecision of current incomplete techniques. Our new deadlock candidate criterion is based on constraints derived from the analysis of the state space of pairs of components. This new characterisation represents an improvement in the accuracy of current incomplete techniques; in particular, the so-called non-hereditary deadlock-free systems (i.e. deadlock-free systems that have a deadlocking subsystem), which are neglected by most incomplete techniques, are tackled by our framework. Furthermore, we demonstrate how SAT checkers can be used to efficiently implement our framework in a way that, typically, scales better than current techniques for deadlock analysis. This is demonstrated by a series of practical experiments.

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Notes

  1. 1.

    Depending on the properties of the underlying communicating system, one might be able to restrict such cycles to proper cycles which have at least three nodes, and where all the nodes are distinct.

  2. 2.

    FDR3 uses a more general representation of a process called a generalised labelled transition system (GLTS). Nevertheless, this extension can be simply converted into a traditional LTS and working with LTS makes our definitions considerably simpler.

  3. 3.

    SDD stands for State Dependency Digraph.

  4. 4.

    There are some significant differences with SLAP: here the propositional formula is satisfied by a possible deadlock, whereas in SLAP the propositional formula is satisfied by a proof of livelock freedom. We might also note that livelock arises from a sequence of states, whereas deadlock arises in a single one.

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Acknowledgments

We are grateful to Jöel Ouaknine and James Worrell for many fruitful discussions concerning this work. The first author is a CAPES Foundation scholarship holder (Process no: 13201/13-1). The second and third authors are partially sponsored by DARPA under agreement number FA8750-12-2-0247.

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Antonino, P., Gibson-Robinson, T., Roscoe, A.W. (2016). Efficient Deadlock-Freedom Checking Using Local Analysis and SAT Solving. In: Ábrahám, E., Huisman, M. (eds) Integrated Formal Methods. IFM 2016. Lecture Notes in Computer Science(), vol 9681. Springer, Cham. https://doi.org/10.1007/978-3-319-33693-0_22

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  • DOI: https://doi.org/10.1007/978-3-319-33693-0_22

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