Abstract
Growing international interest in the development of space missions based on low-cost nano-/microsatellites demands new approaches to the design of reliable, low-cost, reconfigurable digital processing platforms. To meet these requirements, future systems will need to include application-specific processors to handle control-dominated tasks and hardware accelerators to cope with data-intensive workloads. Commercial-Off-The-Shelf (COTS) Field-Programmable Gate Arrays (FPGAs) provide an ideal platform for meeting these requirements with application-specific processors implemented as soft cores along with hardware accelerators on FPGA fabric. However, the main challenge to deploying reconfigurable systems in space is mitigating the impact of radiation-induced Single Event Upsets (SEUs). In considering the design of such heterogeneous systems, we present a survey of techniques commonly employed to guard against soft errors in application-specific processors that are conventionally targeted at ASICs and assess their suitability to FPGA implementation when partial reconfiguration is used to deal with SEUs in logic circuits. Finally, we report on the development of the RUSH payload, to be deployed on the UNSW-EC0 CubeSat due for launch in 2016, to test our design approach.
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References
SpaceWorks (2013) Nano/Microsatellite market assessment. bit.ly/17p9M5F
Asadi H, Tahoori MB, Mullins B, Kaeli D, Granlund K (2007) Soft error susceptibility analysis of SRAM-based FPGAs in high-performance information systems. IEEE Trans Nucl Sci 54(6):2714–2726
Cetin E, Diessel O, Lingkan G, Lai V (2013) Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration. In: Proceedings of the 23rd international conference on field programmable logic and applications (FPL), 2013, pp 1–4
Cetin E, Diessel O, Lingkan G, Lai V (2014) Reconfiguration network design for SEU recovery in FPGAs. In: Proceedings of the 2014 IEEE international symposium on circuits and systems (ISCAS), 2014, pp 1524–1527
QB50 Project Description https://www.qb50.eu/index.php/project-description-obj
LogiCORE IP soft error mitigation controller v4.1 product guide, Xilinx App. Note PG036 2014
Praet JV, Goossens G, Lanneer D, Man HD (1994) Instruction set definition and instruction selection for ASIPs. In: Proceedings of the 7th international symposium on high-level synthesis, IEEE Computer Society Press, 1994, pp 11–16
Tuo L, Shafique M, Ambrose JA, Rehman S, Henkel J, Parameswaran S (2013) RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors. In: Proceedings of the 2013 50th ACM / EDAC / IEEE design automation conference (DAC), 2013, pp 1–7
Tuo L, Ragel R, Parameswaran S (2012) Reli: hardware/software checkpoint and recovery scheme for embedded processors. In: Proceedings of the design, automation & test in Europe conference & exhibition (DATE), 2012, pp 875–880
Ragel RG, Parameswaran S (2006) IMPRES: integrated monitoring for processor reliability and security. In: Proceedings of the 2006 43rd ACM/IEEE design automation conference, 2006, pp 502–505
Reis GA, Chang J, August DI (2007) Automatic instruction-level software-only recovery. IEEE Micro 27(1):36–47
Rehman S, Shafique M, Kriebel F, Henkel J (2011) Reliable software for unreliable hardware: embedded code generation aiming at reliability. In: Proceedings of the 9th international conference on hardware/software codesign and system synthesis (CODES+ISSS), 2011, pp 237–246
Reorda MS, Violante M, Meinhardt C, Reis R (2009) A low-cost SEE mitigation solution for soft-processors embedded in systems on pogrammable chips. In: Proceedings of the design, automation & test in Europe conference & exhibition (DATE ’09), 2009, pp 352–357
Hung-Manh P, Pillement S, Piestrak SJ (2013) Low-overhead fault-tolerance technique for a dynamically reconfigurable softcore processor. IEEE Trans Comput 62(6):1179–1192
Ichinomiya Y, Tanoue S, Amagasaki M, Iida M, Kuga M, Sueyoshi T (2010) Improving the robustness of a softcore processor against SEUs by using TMR and partial reconfiguration. In: Proceedings of the 2010 18th IEEE annual international symposium on field-programmable custom computing machines (FCCM), 2010, pp 47–54
Vavousis A, Apostolakis A, Psarakis M (2013) A Fault tolerant approach for FPGA embedded processors based on runtime partial reconfiguration. J Electron Test 29(6):805–823
Bolchini C, Miele A, Santambrogio MD (2007) TMR and partial dynamic reconfiguration to mitigate SEU faults in FPGAs. In: Proceedings of the 22nd IEEE international symposium on defect and fault-tolerance in VLSI systems, DFT ’07, 2007, pp 87–95
Carmichael C (2001) Triple modular redundancy design techniques for Virtex FPGAs. Technical report, Xilinx Corp., XAPP197 (v1.0)
Pilotto C, Azambuja JR, Kastensmidt FL (2008) Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications. In: Proceedings of the 21st annual symposium on integrated circuits and system design, ACM, 2008, pp 199–204
Johnson JM, Wirthlin MJ (2010) Voter insertion algorithms for FPGA designs using triple modular redundancy. In: Proceedings of the 18th annual ACM/SIGDA international symposium on field programmable gate arrays, ACM, 2010, pp 249–258
VKI, QB50 System requirements and recommendations and interface control document, Issue 3, VKI, 2013
Microsemi Corp., SmartFusion customisable system-on-chip (cSoC) (2013) http://www.actel.com/documents/SmartFusion_DS.PDF
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Cetin, E. et al. (2016). Overview and Investigation of SEU Detection and Recovery Approaches for FPGA-Based Heterogeneous Systems. In: Kastensmidt, F., Rech, P. (eds) FPGAs and Parallel Architectures for Aerospace Applications. Springer, Cham. https://doi.org/10.1007/978-3-319-14352-1_3
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DOI: https://doi.org/10.1007/978-3-319-14352-1_3
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-14351-4
Online ISBN: 978-3-319-14352-1
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