Abstract
We propose a junctionless tunnel FET architecture with a heterostructure at the source/channel interface. We show that the use of a low bandgap material in the source of this device results in significant ON current improvement. We further show that ON current improvement can also be achieved by using a low-k isolation dielectric. The proposed device architecture which combines the merits of both junctionless FETs and Tunnel FETs can be a potential candidate for sub-20 nm technology node.
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References
J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain,P. Razavi, B. O’Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy,and R. Murphy, “Nanowire transistors without junctions,” Nature Nanotechnology, vol. 5, no. 3, pp. 225–229, 2010.
S. Gundapaneni, M. Bajaj, R. K. Pandey, K. V. R. Murali, S. Ganguly, and A. Kottantharayil, “Effect of band-to-band tunneling on junctionless transistors,” IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1023–1029, Apr. 2012.
S. Gundapaneni, S. Ganguly, and A. Kottantharayil, “Bulk planar junctionless transistor (BPJLT): An attractive device alternative for scaling,”Electron Device Letters, IEEE, vol. 32, no. 3, pp. 261 –263, 2011.
H. G. Virani, A. R. B. Rao, and A. Kottantharayil, “Dual-k spacer device architectures for the improvement of performance of hetero structure n-channel tunnel FETs,” IEEE Transactions on Electron Devices, vol. 57,no. 10, pp. 2410–2417, 2010.
B. Ghosh and M. W. Akram, “Junctionless Tunnel Field Effect Transistor”, Electron Device Letters, IEEE, vol. 34, no. 5, pp. 584 –586, 2013.
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Gundapaneni, S., Konar, A., Bajaj, M., Murali, K.V.R.M. (2014). Improved Performance of Junctionless Tunnel FETs with Source/Channel Heterostructure. In: Jain, V., Verma, A. (eds) Physics of Semiconductor Devices. Environmental Science and Engineering(). Springer, Cham. https://doi.org/10.1007/978-3-319-03002-9_73
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DOI: https://doi.org/10.1007/978-3-319-03002-9_73
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-03001-2
Online ISBN: 978-3-319-03002-9
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