Abstract
Quantum-Dot Cellular Automata (QCA) has arisen as a potential option in contrast to CMOS in the late time of nanotechnology. Some appealing highlights of QCA incorporate incredibly low force utilization and dissemination, high gadget pressing thickness, high velocity (arranged by THz). QCA based plans of normal advanced modules were concentrated broadly in the ongoing past. Equality generator and equality checker circuits assume a significant part in blunder discovery and subsequently, go about as fundamental segments in correspondence circuits. In any case, not very many endeavors were made for an efficient plan of QCA based equality generator as well as equality checker circuits up until now. In addition, these current plans need functional feasibility as they bargain a ton with normally acknowledged plan measurements like territory, postponement, intricacy, and manufacture cost. This article depicts new plans of equality generator and equality checker circuits in QCA which beat every one of the current plans as far as previously mentioned measurements. The proposed plans can likewise be effortlessly reached out to deal with an enormous number of contributions with a straight expansion in territory and inactivity.
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References
Compano, R., Molenkamp, L., Paul, D.J.: Technology roadmap for nanoelectronics. In: European Commission IST Programme, Future and Emerging Technologies, pp. 1–104 (2000)
Lent, C.S., Tougaw, P.D., Porod, W., Bernestein, G.H.: Quantum cellular automata. Nanotechnology 4, 49–57 (1993)
Niemer, M.T., Kogge, P.M.: Problems in designing with QCAs: layout = timing. Int. J. Circuit Theory Appl. 29, 49–62 (2001)
Bernstein, G.H., et al.: Magnetic QCA systems. Microelectron. J. 36, 619–624 (2005)
Huang, J., Lombardi, F.: Design and Test of Digital Circuits by Quantum-dot Cellular Automata. Artech House Inc., Norwood (2007)
Lee, S., Cho, K., Choi, S., Kang, S.: A new logic topology-based scan chain stitching for test-power reduction. IEEE Trans. Circuits Syst. II 67(12), 1–5 (2020)
Pomeranz, I.: Extended transparent-scan. IEEE Trans. Very Large Scale Integr. VLSI Syst. 27(9), 2096–2104 (2019)
Navi, K., Sayedsalehi, S., Farazkish, R., Azghadi, M.R.: Five-input majority gate, a new device for quantum-dot cellular automata. J. Comput. Theor. Nanosci. 7, 1546–1553 (2010)
Karmakar, R., Chattopadhyay, S., Kapur, R.: A scan obfuscation guided design for-security approach for sequential circuits. IEEE Trans. Circuits Syst. II Express Briefs 67(3), 1–5 (2020)
Walus, K., Jullien, G.A., Dimitrov, V.S.: RAM design using quantum-dot cellular automata. Nanotechnol. Conf. Trade Show 2, 160–163 (2003)
Kanda, M., Hashizume, M., Ashikin Binti Ali, F., Yotsuyanagi, H., Lu, S.-K.: Open defect detection not utilizing boundary scan flip-flops in assembled circuit boards. IEEE Trans. Compon. Packag. Manuf. Technol. 10(5), 895–907 (2020)
Mukherjee, N., et al.: Time and area optimized testing of automotive ICs. IEEE Trans. Very Large Scale Integr. VLSI Syst. 29(1), 1–13 (2021)
Debnath, B., Das, J.C., De, D., Ghaemi, F., Ahmadian, A., Senu, N.: Reversible palm vein authenticator design with quantum dot cellular automata for information security in nanocommunication network. IEEE Access 8, 174821–174832 (2020)
Kim, J., Lee, S., Kang, S.: Test-friendly data-selectable self-gating (DSSG). IEEE Trans. Very Large Scale Integr. VLSI Syst. 27(8), 1972–1976 (2019)
Walus, K., Dysart, T.J., Jullien, G.A., Budiman, R.A.: QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata. IEEE Trans. Nanotechnol. 3(1), 26–31 (2004)
Mukhopadhyay, D., Dutta, P.: A study on energy optimized 4 dot 2 electron two dimensional quantum dot cellular automata logical reversible flip-flops. Microelectron. J. 46, 519–530 (2015)
Kim, K., Ibtesam, M., Kim, D., Jung, J., Park, S.: CAN-based aging monitoring technique for automotive ASICs with efficient soft error resilience. IEEE Access 8, 22400–22410 (2020)
Ottavi, M., Vankamamidi, V., Lombardi, F., Pontarelli, S.: Novel memory designs for QCA implementation. In: The fifth IEEE Conference on Nanotechnology, pp. 545–548 (2005)
Debnath, B., et al.: Security analysis with novel image masking based quantum-dot cellular automata information security model. IEEE Access 8, 1–4 (2020)
Datta, K., Mukhopadhyay, D., Dutta, P.: Comprehensive study on the performance comparison of logically reversible and irreversible parity generator and checker designs using two-dimensional two-dot one-electron QCA. Microsyst. Technol. 25(5), 1659–1667 (2017). https://doi.org/10.1007/s00542-017-3445-2
Datta, K., Mukhopadhyay, D., Dutta, P.: Comprehensive design and analysis of Gray code counters using 2-dimensional 2-dot 1-electron QCA. Microsyst. Technol. 28, 1–19 (2018). https://doi.org/10.1007/s00542-018-3818-1
Ghosh, M., Mukhopadhyay, D., Dutta, P.: A novel parallel memory design using 2 dot 1 electron QCA. In: IEEE 2nd International Conference on Recent Trends in Information Systems, pp. 485–490 (2015)
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Tapna, S., Chakrabarti, K., Mukhopadhyay, D. (2022). A Secure Communication Gateway with Parity Generator Implementation in QCA Platform. In: Mukhopadhyay, S., Sarkar, S., Dutta, P., Mandal, J.K., Roy, S. (eds) Computational Intelligence in Communications and Business Analytics. CICBA 2022. Communications in Computer and Information Science, vol 1579. Springer, Cham. https://doi.org/10.1007/978-3-031-10766-5_15
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