Abstract
The topic of this paper is the precise modelling of all known forms of asynchronous controller and arbiter behaviour from a causal point of view, and for the purpose of synthesis. In addition to the causal relations between input and output edges provided by the conventional STG (dependence, independence, and exclusion) two forms of pseudo-causality, b-and tcb-concurrency (in signal-tracking behaviour), causal linkage (in multiple input changes and bursts), and race causality (temporal relations as causes, in critical input races) are found to be needed. For their Petri net representation, tc-labelled read and inhibitor arcs, transitions labelled with joint events, and decision transitions representing internal events are introduced. Based on these results, a generalized STG for the first time allows precise causal specifications of all known forms of arbiter behaviour, in particular of “three-way” arbiters that recognize and respond to simultaneous requests with a specific reaction. Several circuit examples are discussed.
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References
L.Y. Rosenblum and A.V. Yakovlev. Signal graphs: from self-timed to timed ones. Proceedings of the International Workshop on Timed Petri Nets, Torino, Italy, 1985.
T.-A. Chu. On the models for designing VLSI asynchronous digital systems. Integration: the VLSI journal, 4, pp. 99–113, 1986.
A. Kondratyev, M. Kishinevsky, and A. Yakovlev. Hazard-Free Implementation of Speed-Independent Circuits. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, Nr. 9, pp. 749–771, September 1998.
D.E. Muller and W.C. Bartky. A theory of asynchronous circuits. In Annals of Computing Laboratory of Harvard University, 204–243, 1959.
P. Vanbekbergen, B. Lin, G. Goossens, and H. De Man. A generalized state assignment theory for transformations on signal transition graphs. Proc. ICCD’92, MA, Oct. 1992.
J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Taubin, and A. Yakovlev. Lazy transition systems: application to timing optimizations of asynchronous circuits. Proc. ICCAD’98, San Jose, CA, USA, Nov. 1998.
A. Davis, B. Coates, and K. Stevens. The Post Office Experience: Designing a Large Asynchronous Chip. Proc. 26th Annu. Hawaii Int. Conf on Systems Sciences, 1993.
S. M. Nowick. Automatic Synthesis of Burst-Mode Asynchronous Controllers. PhD thesis, Stanford University, 1993.
K. Y. Yun. Synthesis of Asynchronous Controllers for Heterogeneous Systems. PhD thesis, Stanford University, 1994.
J. Beister, G. Eckstein, and R. Wollowski. From STG to Extended-Burst-Mode Machines. Proc. 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems, Barcelona, April 1999.
S. Wendt. Using Petri nets in the design process for interacting asynchronous sequential circuits. Proc. IFAC-Symposium on Discrete Systems, vol. 2:130–138, Dresden, 1977.
S. H. Unger. Asynchronous Sequential Switching Circuits. R. E. Krieger, reprint 1983 (original edition 1969 ).
J. Cortadella, L. Lavagno, P. Vanbekbergen, and A. Yakovlev. Designing asynchronous circuits from behavioural specifications with internal conflicts. UPC/DAC TR-RR 94/08.
G. Chiola, S. Donatelli, and G. Franceschinis. Priorities, Inhibitor Arcs, and Concurrency in P/T nets. Proc. ICATPN’91, pp. 182–205, Aarhus, Denmark, 1991.
S. Christensen and N.D. Hansen. Coloured Petri nets extended with place capacities, test arcs and inhibitor arcs“, ICATPN’93, LNCS 691, pp. 186–205, Springer, 1993.
R. Janicki and M. Koutny. Semantics of Inhibitor Nets. Information and Computation, 123, 1995.
G.M. Pinna and A. Poigné. On the nature of events: another perspective in concurrency. Theoretical Computer Science, 138, pp. 425–454, 1995.
J.-P. Katoen. Causal behaviours and nets. ICATPN’95, LNCS 935, Springer, 1995.
J.-P. Katoen, R. Langerak, D. Latella and E. Brinksma. On specifying real-time systems in a causality-based setting. Formal techniques in real time and fault tolerant systems: 4th International Symposium, LNCS 1135, pp. 258–277, Springer, 1996.
R. Janicki. A formal semantics for concurrent systems with a priority relation. Acta Informatica, 24, pp. 33–55, 1987.
R. Wollowski. Entwurfsorientierte Petrinetz-Modellierung des Schnittstellen-Sollverhaltens asynchroner Schaltwerksverbünde. Doctoral thesis, Univ. of Kaiserslautern, Dep. of Electrical Engineering, 1997 (Shaker Verlag, Aachen, Germany, 1997 ).
P. Vanbekbergen, C. Ykman-Couvreur, B. Lin and H. de Man. A generalized signal transition graph model for specification of complex interfaces. Proc. European Design and Test Conference, 378–384, IEEE computer society press, 1994.
R. Wollowski, J. Beister. Precise Petri Net Modelling of Critical Races in Asynchronous Arbiters and Synchronizers. Proc. HWPN’98 within 19th ICATPN, Lisbon, June 1998.
R. Wollowski and J. Beister. Comprehensive Causal Specification of Asynchronous Circuit Behaviour: a Generalized STG. Proc. HWPN’99 within 20th ICATPN, Williamsburg, June 1999.
R. Wollowski and J. Beister. A Generalized STG. Technical report B-1–99, University of Kaiserslautern, Department of Electrical Engineering, 1999.
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Wollowski, R., Beister, J. (2000). Comprehensive Causal Specification of Asynchronous Controller and Arbiter Behaviour. In: Yakovlev, A., Gomes, L., Lavagno, L. (eds) Hardware Design and Petri Nets. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3143-9_1
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