Modeling of Carrier Transport in the Finite Collision Duration Regime: Effects in Submicron Semiconductor Devices

Abstract

Over the last two decades, the electronics industry has re sponded to market forces by producing less expensive, but more complex and sophisticated, integrated circuits by large-scale-integration (LSI). The growth of LSI has in fact been phenomenal, and the application of special integrated circuits and microprocessors has blossomed. In fact, the complexity of these circuits, where complexity is defined here by the number of individual devices on an integrated circuit chip, has approximately doubled each year over this time span. There are, of course, several factors which contribute to this increase in complexity, including major effects arising from increased die size, increased circuit cleverness, and reduced device size (Moore, 1975). This latter factor, reduction of the individual feature size in a device, is of paramount importance and dimensions are currently down to the 1–2 micrometer range. Progress in the micro-electronics industry is strongly coupled with the ability to continue to make ever increasing numbers of smaller, and more clever, devices on a single chip; i.e., the move toward very-large-scale-integration (VLSI) will be of paramount importance to this continued progress. It is apparent that extrapolation of today’s technology will produce individual devices whose dimensions are of the order of 0.2–0.5 micrometers (Ballantyne, 1978).