Abstract
Low power LSI memory technology is becoming an increasingly important and growing area of electronics. In particular, low power RAM technology is a major area of this technology. Rapid and remarkable progress has been made in power reduction for RAM subsystems and there is strong potential for future improvement. This progress has even formed the basis for power reduction for other important memory types such as flash memory and ROM. Low power RAM technology includes low-power chip technology, multi-data-bit chip-configurations in which a large number of data-bits are processed simultaneously, small package technology, and low voltage chip-to-chip interfaces. Low power chip technology has contributed mainly to subsystem power reduction. Multi-data-bit chip-configuration has become more popular as chip memory capacity increases, since it effectively reduces subsystem power with resultant lower chip count for a fixed subsystem memory capacity. In addition to lowered chip counts, small package technology combined with high-density chip technology has reduced AC power, with less capacitance for address lines, control lines and data input/output bus lines on memory boards. Lowering voltage swing on data-bus lines reduces the AC power which is always increasing, in line with the strong requirement for higher data-throughput for memory subsystems. In any event, RAM chip power is a primary concern of the subsystem designer, since it dominates subsystem power.
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References
K. Itoh, K. Sasaki and Y. Nakagome, “Trends in Low-Power RAM Circuit Technologies,” Proc IEEE., April 1995
Y. Nakagome et al., “An experimental 1.5-V 64-Mb DRAM,” IEEE J. Solid-State Circuits, vol. 26, no. 3, pp. 465–472, April 1991.
K. Satoh et al., “A 4Mb pseudo-SRAM operating at 2.6¿1 V with 3uA data-retention current,” ISSCC Dig. Tech. Papers,26 pp. 268–269, Feb. 1991.
M. Matsumiya et al., “A 15ns 16Mb CMOS SRAM with Reduced Voltage Amplitude Data Bus,” ISSCC Dig. Tech. Papers, 26pp. 214–215, Feb. 1992.
HITACHI MEMORY CATALOGS, Aug. 1993 and Aug. 1994.
M. Lamson et al., “Lead-On-Chip Technology for High Performance Packaging,” Proc. 43rd Electronic Components and Technology Conference, 26pp.1045–1050, June, 1993.
M. Taguchi, “High-Speed, Small-Amplitude I/O Interface Circuits for Memory Bus Application,” IEICE Trans. Electron., vol. E77-C, No.12, pp. 1944–1950, Dec. 1994.
K. Kimura et al., “Power reduction techniques in megabit DRAM’s,” IEEE J. Solid-State Circuits, vol.SC-21, pp. 381–389, June 1986.
K. Itoh, “Trends in megabit DRAM circuit design,” IEEE J. Solid-State Circuits, Vol. 25, pp. 778–789, June 1990.
M. Aoki and K. Itoh,“ Low-Voltage, Low-Power ULSI Circuit Techniques,” IEICE,Transactions on Electronics, vol. E77-C, No. 8, pp. 1351–1360, August 1994.
K. Itoh et al., “An experimental 1Mb DRAM with on-chip voltage limiter,” ISSCC Dig. Tech. Papers, 8pp. 106–107, Feb. 1984.
T. Sugibayashi et al., “A 30ns 256Mb DRAM with multi-divided array structure,” ISSCC Dig.Tech. Papers, 8pp. 50–51, Feb. 1993.
K. Itoh, “Reviews and prospects of deep sub-micron DRAM technology,” International Conf. Solid State Devices and Materials, Yokohama,8 pp. 468–471, Aug. 1991.
N.C.C. Lu and H. Chao, “Half-VDD bit-line sensing scheme in CMOS DRAM,” IEEE J. Solid-State Circuits, vol.SC-19, pp. 451–454, Aug. 1984.
H. Tanaka et al., “Stabilization of voltage limiter circuit for high-density DRAM’s using pole-zero compensation,” IEICE Trans. Electron., vol.E75-C, no.11, pp. 1333–1343, Nov. 1992.
M. Horiguchi et al., “Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test,” IEEE J. Solid-State Circuits, vol.26, no.11, pp. 1544–1549, Nov. 1991.
S. M. Sze, “Physics of Semiconductor Devices (2nd ed.),” Wiley, New York, 1981.
Y. P. Tsividis, “Operation and Modeling of the MOS Transistor,” New York, McGraw-Hill, 1988.
M. Horiguchi et al., “Switched-source-impedance CMOS circuit for low standby sub-threshold current giga-scale LSI’s,” IEEE J. Solid-State Circuits, vol.28, pp. 1131–1135, Nov. 1993.
T. Sakata et al., “Subthreshold-current reduction circuits for multi-gigabit DRAM’s,” Symp. VLSI Circuits Dig. Tech. Papers, 28pp. 45–46, May 1993.
T. Kawahara et al., “Subthreshold current reduction for decoded-driver by self biasing,” IEEE J. Solid-State Circuits, vol.28, no.11, pp. 1136–1144, Nov. 1993.
T. Sakata et al., “Two-dimensional power-line selection scheme for low subthresholdcurrent multi-gigabit DRAMs,” ESSCIRC Dig. Tech. Papers,28 pp. 33–36, Sept. 1993.
M. Asakura et al., “A 34ns 256Mb DRAM with Boosted Sense-Ground Scheme,” ISSCC Dig. Tech. Papers, 28pp. 140–141, Feb. 1994.
M. Takada, et al., “Reviews and Prospects of SRAM Technology,” IEICE Transactions, vol. E74, No. 4, pp. 827–838, April 1991.
K. Sasaki, “High-Speed, Low-Voltage Design for High-Performance Static RAMs,” Proc. of Tech. Papers, VLSI Technology, System, and Applications, 28pp. 292–296, May 1993.
M. Yoshimoto, et al., “A 64Kb CMOS RAM with Divided Word Line Structure,” ISSCC Dig. Tech. Papers, 28pp. 58–59, Feb. 1983.
O. Minato, et al., “A 20ns 64K CMOS RAM,” ISSCC Dig. Tech. Papers, 28pp. 222–223, Feb. 1984.
K. Sasaki, et al., “A 9-ns 1-Mbit CMOS RAM,” IEEE J. Solid-State Circuits, vol. 24, pp. 1219–1225, Oct. 1989.
K. Sasaki, et al., “A 7Mb 140mW CMOS SRAM with Current Sense Amplifier,” ISSCC Dig. Tech. Papers,28pp. 208–209, Feb. 1992.
H. W. Johnson and M. Graham, “High-Speed Digital Design,” Prentice-Hall, 1993.
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Itoh, K. (1996). Low Power Memory Design. In: Rabaey, J.M., Pedram, M. (eds) Low Power Design Methodologies. The Springer International Series in Engineering and Computer Science, vol 336. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2307-9_8
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DOI: https://doi.org/10.1007/978-1-4615-2307-9_8
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