Abstract
Three-dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues in future 3D multicore systems. However, the thermal problems of 3D NoC are more serious than 2D NoC due to stacking dies. To keep the temperature below a certain thermal limit, many approaches of run-time thermal management were proposed. In this chapter, we will introduce some design concepts of traffic- and thermal-aware routing algorithms, which aim at minimize the performance impact caused by the run-time thermal managements. The investigative approaches can mitigate the design challenges of 3D NoC systems. Without the enhancement of cooling devices, the 3D NoC system can still be thermal-safe. Besides, the advantages of 3D integration are preserved, because the thermal-limited performance back-off is reduced.
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References
J. Davis, R. Venkatesan, A. Kaloyeros et al., Interconnect limits on Gigascale Integration (GSI) in the 21st century. Proc. IEEE 89(3), 305–324 (2001)
S. Kumar, A. Jantsch, J.P. Soininen et al., A network on chip architecture and design methodology, in Proceedings of the IEEE International Symposium on VLSI, Vancouver, 2002, pp. 105–112
Y. Hoskote, S. Vangal, A. Singh et al., A 5-GHz mesh interconnect for a teraflops processor. IEEE Micro 27(5), 51–61 (2007)
J. Howard, S. Dighe, Y. Hoskote et al., A 48-Core IA-32 Message-passing processor with DVFS in 45nm CMOS, in IEEE International Solid-State Circuit Conference Digest of Technical Papers (ISSCC), San Francisco, 2010, pp. 70–11
S. Bell, B. Edwards, J. Amann et al., TILE64-Processer: A 64-Core SoC Mesh Interconnect, in IEEE International Solid-State Circuit Conference Digest of Technical Papers (ISSCC), San Francisco, 2008, pp. 3–7
Y. Xie, J. Cong, S. Sapatnekar, Three-Dimensional Integrated Circuit Design (Springer, Heidelberg, 2009)
A.W. Topol, D. Tulipe, L. Shi et al., Three-dimensional integrated circuits. IBM J. Res. Dev. 50(4.5), 491–506 (2006)
B.S. Feero, P.P. Pande, Networks-on-chip in a three dimensional environment: a performance evaluation. IEEE Trans. Comput. 58(1), 32–45 (2009)
L. Shang, L. Peh, A. Kumar, N.K. Jha, Thermal modeling, characterization and management of on-chip networks, in Proceedings of the IEEE/ACM International of Symposium on Microarchitecture (Micro), Portland, 2004, pp. 67–78
W. Hung, C. Addo-Quaye, T. Theocharides et al., Thermal-aware IP virtualization and placement for networks-on-chip architecture, in Proceedings of the IEEE International Conference on Computer Design (ICCD), San Jose, 2004, pp. 430–437
G.M. Link, N. Vijaykrishnan, Hotspot prevention through runtime reconfiguration in network-on-chip, in Proceedings of the IEEE Conference on Design, Automation, and Test in Europe (DATE), Munich, 2005, pp. 648–649
K.Y. Jheng, C.H. Chao, H.Y. Wang, A.Y. Wu, Traffic-thermal mutual-coupling co-simulation platform for three-dimensional network-on-chip, in Proceedings of the IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, 2010, pp. 135–138
G. Hinton, D. Sager, M. Upton et al., The micro-architecture of the Pentium 4 processor, Intel Technology Journal, 2001
C.H. Chao, K.Y. Jheng, H.Y. Wang et al., Traffic- and thermal-aware run-time thermal management scheme for 3D NoC system, in IEEE International Symposium on Network-on-Chip (NOCS), Grenoble, 2010, pp. 223–230
C.H. Chao, K.C. Chen, T.C. Yin et al., Transport layer assisted routing for run-time thermal management of 3D NoC systems, ACM Trans. Embedd. Comput. Syst., 13, 1, Article 11 (August 2013), 22 pages
K.C. Chen, S.-Y. Lin, H.-S. Hung, A.-Y. Wu, Topology-Aware Adaptive Routing for Non-Stationary Irregular Mesh in Throttled 3D NoC Systems, IEEE Transactions on Parallel and Distributed Systems, 24(10), 2109–2120 (2013)
G.M. Ghiu, The odd-even turn model for adaptive routing. IEEE Trans. Parallel Distrib. Syst. 11(7), 729–738 (2000)
U.Y. Ogras, J. Hu, R. Marculescu, Key research problems in NoC design: a holistic perspective, in Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis (CODES+ISSS), Jersey, 2005, pp. 69–74
K.C. Chen, S.Y. Lin, H.S. Hung, A.Y. Wu, Topology-aware adaptive routing for non-stationary irregular mesh in throttled 3D NoC systems (early access on IEEE Transactions on Parallel and Distributed Systems, 2013)
S.Y. Lin, T.C. Yin, H.Y. Wang, A.Y. Wu, Traffic-and thermal-aware routing for throttled three-dimensional network-on-chip system, in Proceedings of the IEEE International Symposium VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, 2011, pp. 320–323
G. Ascia, V. Catania, M. Palesi, D. Patti, Neighbors-on-path: a new selection strategy for on-chip networks, in Proceedings of the IEEE/ACM/IFIP Workshop Embedded Systems for Real Time Multimedia, Seoul, 2006, pp. 79–84
P. Gratz, B. Grot, S.W. Keckler, Regional congestion awareness for load balance in networks-on-chip, in Proceedings of the IEEE Symposium High Performance Computer Architecture (HPCA), Salt Lake City, 2008, pp. 203–214
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Chen, KC., Chao, CH., Lin, SY., Wu, AY.(. (2014). Traffic- and Thermal-Aware Routing Algorithms for 3D Network-on-Chip (3D NoC) Systems. In: Palesi, M., Daneshtalab, M. (eds) Routing Algorithms in Networks-on-Chip. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-8274-1_12
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DOI: https://doi.org/10.1007/978-1-4614-8274-1_12
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