Abstract
The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) has made them vehicles of choice for both prototypes and final products requiring on-chip multi-core, heterogeneous and reconfigurable systems. Multiple cores can be embedded as hard- or soft-macros, have customizable instruction sets, multiple distributed RAMs and/or configurable interconnections. Their flexibility allows them to achieve orders of magnitude better performance than conventional computing systems via customization. Programming these systems, however, is extremely cumbersome and error-prone and as a result their true potential is only achieved very often at unreasonably high design efforts. This project covers developing, implementing and evaluating a novel compilation and synthesis system approach for FPGA-based platforms. We rely on Aspect-Oriented Specifications to convey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development as well as program and application portability. We leverage Aspect-Oriented specifications and a set of transformations to generate an intermediate representation suitable to hardware mapping. A programming language, LARA, will allow the exploration of alternative architectures and design patterns enabling the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. We will evaluate the effectiveness of the proposed approach using partner-provided codes from the domain of audio processing and real-time avionics. We expect the technology developed in REFLECT to be integrated by our industrial partners, in particular by ACE, a leading compilation tool supplier for embedded systems, and by Honeywell, a worldwide solution supplier of embedded high-performance systems.
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Notes
- 1.
The term is used herein in a more generic way than in [16].
- 2.
In practice, design patterns try to fulfill high level requirements that require a global strategy to be accomplished. The selection of the strategies is based on heuristics extracted from good design practices.
- 3.
AspectJ [17], a well-known AOP approach for Java, uses pointcut and advice as operators.
- 4.
They can refer to the entire application, a specific function, all or a specific loop, or even a specific location in the code for which an annotated label in the C code is used.
- 5.
E.g., the C-to-VHDL generator used in the back-end of CoSy may not support all C constructs.
- 6.
It includes annotations of customized bit-widths, statement latencies and scheduling, etc.
- 7.
During the design flow a join point might be removed by a previous tool’s action or might be different from the original when a previous tool transforms the code.
- 8.
LARA is currently being designed and the version presented here uses and extends some of the concepts proposed in [22].
- 9.
Strength reduction can also be applied to optimize the calculation of array indexing of z, i.e., 64*j used in z[i + 64*j] and in z[i + 1+64*j], lines 11 and 12 in Fig. 9. The expression 64*j can be translated to j < < 6 which can be implemented in hardware with the 26 least significant bits of j concatenated with six zeros.
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Cardoso, J.M.P. et al. (2011). REFLECT: Rendering FPGAs to Multi-core Embedded Computing. In: Cardoso, J., Hübner, M. (eds) Reconfigurable Computing. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0061-5_11
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