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Architectural Yield Optimization

  • Chapter
Wafer Scale Integration

Abstract

Fabrication of integrated circuits or systems that span an entire wafer or a significant part of a wafer have held the interest of a number of semiconductor researchers [1]. The expected benefits of smaller size, increased reliability, reduced cost, shorter signal delays, and simpler packaging are significant. Unfortunately, most of the previously reported attempts have been surpassed by increased density, improved circuitry, and better packaging of conventional integrated circuits.

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Authors
  1. N. R. Strader
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  2. J. C. Harden
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Editor information

Editors and Affiliations

  1. TRW Defense Systems Group, Redondo Beach, California, USA

    Earl E. Swartzlander Jr.

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© 1989 Kluwer Academic Publishers

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Strader, N.R., Harden, J.C. (1989). Architectural Yield Optimization. In: Swartzlander, E.E. (eds) Wafer Scale Integration. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1621-3_3

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  • DOI: https://doi.org/10.1007/978-1-4613-1621-3_3

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4612-8896-1

  • Online ISBN: 978-1-4613-1621-3

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