Skip to main content
SpringerLink
Log in

Hardware Metering: A Survey

  • Chapter
  • First Online:
Introduction to Hardware Security and Trust

Abstract

This chapter provides the first comprehensive overview of hardware integrated circuits (IC) protection by metering. Hardware metering, or IC metering refers to mechanisms, methods, and protocols that enable tracking of the ICs postfabrication. Metering is particularly needed in the horizontal semiconductor business model where the design houses outsource their fabrication to (mostly offshore) contract foundries to mitigate the manufacturing and labor costs. The designers and/or the design intellectual property (IP) holders are vulnerable to piracy and overbuilding attacks due to the transparency of their designed IP to the foundry that requires a complete description of the design components and layout to fabricate the chips. Because of the prevalence of counterfeit and overbuilt items, and the widespread usage of ICs in a variety of important applications, the problem has recently gained an increased attention by the industry, government, and research community. Post-silicon identification and tagging of the individual ICs fabricated by the same mask is a precursor for metering: In passive metering, each ICs is specifically identified, either in terms of its functionality or by other forms of unique identification. The identified ICs may be matched against their record in a preformed database that could reveal unregistered ICs or overbuilt ICs (in case of collisions). In active metering, not only the ICs are uniquely identified but also parts of the chip’s functionality can be only accessed, locked (disabled), or unclocked (enabled) by the designer and/or IP rights owners with a high level knowledge of the design that is not transferred to the foundry. We provide a systematic view of the field, along with the first detailed taxonomy and descriptions of the various passive and active hardware metering methods available.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 99.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 129.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 179.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Mouli C, Carriker W (2007) Future fab: How software is helping intel go nano–and beyond. IEEE Spectrum 44(3): 38-43

    Article  Google Scholar 

  2. Santo B (2007) Plans for next-gen chips imperiled. IEEE Spectrum 44(8): 12–14

    Article  Google Scholar 

  3. Defense Science Board (DSB) study on high performance microchip supply (2005) http://www.acq.osd.mil/dsb/reports/ADA435563.pdf

  4. Managing the risks of counterfeiting in the information technology industry (2005) White paper by KPMG and the alliance for gray market and counterfeit abatement (AGMA)

    Google Scholar 

  5. Koushanfar F, Qu G, Potkonjak M (2001) Intellectual property metering. In: International Workshop on Information Hiding (IHW), Springer, Berllin, Heidelberg, New York, pp 81–95

    Google Scholar 

  6. Koushanfar F, Qu G (2001) Hardware metering. In: Design Automation Conference (DAC), Design Automation Conference (DAC), pp 490–493

    Google Scholar 

  7. Lofstrom K, Daasch WR, Taylor D (2000) IC identification circuit using device mismatch. In: International Solid-State Circuits Conference (ISSCC), pp 372–373

    Google Scholar 

  8. Gassend B, Clarke D, van Dijk M, Devadas S (2002) Silicon physical random functions. In: CCS, pp 148–160

    Google Scholar 

  9. Qu G, Potkonjak M (2003) In: Intellectual Property Protection in VLSI Design. Springer, Kluwer Publishing, New York, ISBN 1-4020-7320-8

    Google Scholar 

  10. Kirovski D, Potkonjak M (1999) Localized watermarking: methodology and application to operation scheduling. In: The International Conference on Computer-Aided Design (ICCAD), pp 596–599

    Google Scholar 

  11. Lach J, Mangione-Smith W, Potkonjak M (1998) Signature hiding techniques for FPGA intellectual property protection. In: The International Conference on Computer-Aided Design (ICCAD), pp 186–189

    Google Scholar 

  12. Torunoglu I, Charbon E (2000) Watermarking-based copyright protection of sequential functions. IEEE J Solid-State Circ (JSSC) 35(3): 434–440

    Article  Google Scholar 

  13. Oliveira A (2001) Techniques for the creation of digital watermarks in sequential circuit designs. IEEE Trans Comput Aided Des Integr Circ Syst (TCAD) 20(9): 1101–1117

    Article  Google Scholar 

  14. Koushanfar F, Hong I, Potkonjak M (2005) Behavioral synthesis techniques for intellectual property protection. ACM Trans Des Autom Electron Syst (TODAES) 10(3): 523–545

    Article  Google Scholar 

  15. Koushanfar F, Alkabani Y (2010) Provably secure obfuscation of diverse watermarks for sequential circuits. In: International Symposium on Hardware-Oriented Security and Trust (HOST), pp 42–47

    Google Scholar 

  16. Holcomb D, Burleson W, Fu K (2009) Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Transactions on Computers 58(9): 1198–1210

    Article  MathSciNet  Google Scholar 

  17. Devadas S, Gassend B (2002) Authentication of integrated circuits. Application in US Patent 7,840,803, 2010

    Google Scholar 

  18. Alkabani Y, Koushanfar F, Kiyavash N, Potkonjak M (2008) Trusted integrated circuits: a nondestructive hidden characteristics extraction approach. In: Information Hiding conference (IH). Springer, Berlin, Heidelberg, New York, pp 102–117

    Google Scholar 

  19. Alkabani Y, Koushanfar F (2007) Active hardware metering for intellectual property protection and security. In: USENIX Security Symposium, pp 291–306

    Google Scholar 

  20. Koushanfar F (2011) Provably Secure Active IC Metering Techniques for Piracy Avoidance and Digital Rights Management. In: IEEE Transactions on Information Forensics and Security (TIFS), to appear

    Google Scholar 

  21. Alkabani Y, Koushanfar F, Potkonjak M (2007) Remote activation of ICs for piracy prevention and digital right management. In: The International Conference on Computer-Aided Design (ICCAD), pp 674–677

    Google Scholar 

  22. Huang J, Lach J (2008) IC activation and user authentication for security-sensitive systems. In: International Symposium on Hardware-Oriented Security and Trust (HOST), pp 76–80

    Google Scholar 

  23. Roy J, Koushanfar F, Markov I (2008) EPIC: Ending piracy of integrated circuits. In: Design Automation and Test in Europe (DATE), pp 1069–1074

    Google Scholar 

  24. Roy J, Koushanfar F, Markov I (2008) Protecting bus-based hardware IP by secret sharing. In Design Automation Conference (DAC), pp 846–851

    Google Scholar 

  25. Roy J, Koushanfar F, Markov I (2010) Ending piracy of integrated circuits. IEEE Comput 43: 30–38

    Google Scholar 

  26. Pentium III wikipedia page, http://en.wikipedia.org/wiki/pentium_iii

  27. Pentium III serial numbers, http://www.pcmech.com/article/pentium-iii-serial-numbers/

  28. Potkonjak M, Koushanfar F (2009) Identification of integrated circuits. US Patent Application 12/463,984; Publication Number: US 2010/0287604 A1, May

    Google Scholar 

  29. Koushanfar F, Boufounos P, Shamsi D (2008) Post-silicon timing characterization by compressed sensing. In: The International Conference on Computer-Aided Design (ICCAD), pp 185–189

    Google Scholar 

  30. Shamsi D, Boufounos P, Koushanfar F (2008) Noninvasive leakage power tomography of integrated circuits by compressive sensing. In: International Symposium on Low Power Electronic Design (ISLPED), pp 341–346

    Google Scholar 

  31. Potkonjak M, Nahapetian A, Nelson M, Massey T (2009) Hardware Trojan horse detection using gate-level characterization. In: Design Automation Conference (DAC), pp 688–693

    Google Scholar 

  32. Nelson M, Nahapetian A, Koushanfar F, Potkonjak M (2009) SVD-based ghost circuitry detection. In: Information Hiding (IH), pp 221–234

    Google Scholar 

  33. Alkabani Y, Koushanfar F (2009) Consistency-based characterization for ICTrojan detection. In: International Conference on Computer Aided Designs (ICCAD), pp 123–127

    Google Scholar 

  34. Wei S, Meguerdichian S, Potkonjak M (2010) Gate-level characterization: foundations and hardware security applications. In: Design Automation Conference (DAC), pp. 222–227

    Google Scholar 

  35. Koushanfar F, Mirhoseini A (2011) A unified submodular framework for multimodal IC Trojan detection. In: IEEE Transactions on Information Forensics and Security (TIFS): 6(1): pp. 162–174

    Google Scholar 

  36. Helinski R, Acharyya D, Plusquellic J (2010) Quality metric evaluation of a physical unclonable function derived from an ICs power distribution system. In: Design Automation Conference (DAC), pp. 240–243

    Google Scholar 

  37. Helinski R, Acharyya D, Plusquellic J (2010) Quality metric evaluation of a physical unclonable function derived from an IC’s power distribution system. In: Design Automation Conference, (DAC), pp 240–243

    Google Scholar 

  38. Rührmair U, Devadas S, Koushanfar F (2011) Book chapter in introduction to hardware security and trust. In: Tehranipoor M, Wang C (eds.) Chapter 7: Security based on Physical Unclonability and Disorder. Springer, Berlin, Heidelberg, New York

    Google Scholar 

  39. Barak B, Goldreich O, Impagliazzo R, Rudich S, Sahai A, Vadhan S, Yang K (2001) On the (im)possibility of obfuscating programs. In: Advances in Cryptology (CRYPTO), pp 1–18

    Google Scholar 

  40. Yuan L, Qu G (2004) Information hiding in finite state machine. In: Information Hiding Conference (IH), Springer, Berlin, Heidelberg, New york, pp 340–354

    Google Scholar 

  41. Chakraborty R, Bhunia S (2008) Hardware protection and authentication through netlist level obfuscation. In: The International Conference on Computer-Aided Design (ICCAD), pp 674–677

    Google Scholar 

  42. Alkabani Y, Koushanfar F (2007) Active control and digital rights management of integrated circuit IP cores. In: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pp. 227–234

    Google Scholar 

  43. Maes R, Schellekens D, Tuyls P, Verbauwhede I (2009) Analysis and design of active IC metering schemes. In: International Symposium on Hardware-Oriented Security and Trust (HOST), pp 74–81

    Google Scholar 

  44. Baumgarten A, Tyagi A, Zambreno J (2010) Preventing IC piracy using reconfigurable logic barriers. IEEE Design & Test of Computers 27: 66–75

    Article  Google Scholar 

  45. Koushanfar F (2011) Integrated circuits metering for piracy protection and digital rights management: an overview, Great Lake Symposium on VLSI (GLS-VLSI), pp. 449–454

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Electrical and Computer Engineering Department, Rice University, Houston, Texas, 77251-1892, USA

    Farinaz Koushanfar

Authors
  1. Farinaz Koushanfar
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Farinaz Koushanfar .

Editor information

Editors and Affiliations

  1. , ECE Dept., University of Connecticut, Fairfield Way 371, Storrs, 06269, Connecticut, USA

    Mohammad Tehranipoor

  2. Computing and Information Science Div., Engineering Sciences Directorate, Triangle Park, 27709-2211, North Carolina, USA

    Cliff Wang

Rights and permissions

Reprints and permissions

Copyright information

© 2012 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Koushanfar, F. (2012). Hardware Metering: A Survey. In: Tehranipoor, M., Wang, C. (eds) Introduction to Hardware Security and Trust. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-8080-9_5

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-8080-9_5

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4419-8079-3

  • Online ISBN: 978-1-4419-8080-9

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation