Skip to main content

A unified software pipeline construction scheme for modulo scheduled loops

  • Software
  • Conference paper
  • First Online:
Parallel Computing Technologies (PaCT 1997)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1277))

Included in the following conference series:

Abstract

We present a software pipeline construction scheme for DO-loops, while-loops, and loops with multiple exits, which unifies, simplifies, and generalizes, the separate techniques previously required to build a complete software pipeline from a local schedule computed by modulo scheduling. In the setting of this software pipeline construction scheme, we demonstrate a simple way of implementing a general form of modulo expansion. Then we introduce inductive relaxation, a technique that replaces generalized modulo expansion when the variable to expand is a simple induction. These techniques do not require any architectural support from the target processor, and have been extensively tested as part of the software pipeliner that comes with the 3.0 compiler releases for the Cray T3ETM massively parallel computer.

On leave from the CEA CEL-V, 94195 Villeneuve St Georges cedex France. Part of this research was funded by the DGA grant ERE/SC NĀ° 95-1137/A000/DRET/DS/SR.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. V. H. Allan, R. Jones, R. Lee, S. J. Allan ā€œSoftware Pipeliningā€ ACM Computing Surveys, Sep. 1995.

    Google ScholarĀ 

  2. R. L. Sites ā€œAlpha AXP Architectureā€ Digital Technical Journal, vol. 4, no. 2, 1992.

    Google ScholarĀ 

  3. J. C. Dehnert, R. A. Towle ā€œCompiling for Cydra 5ā€ Journal of Supercomputing, vol. 7, pp. 181ā€“227, May 1993.

    Google ScholarĀ 

  4. B. Dupont de Dinechin ā€œInsertion Scheduling: An Alternative to List Scheduling for Modulo Schedulersā€, Proceedings of 8th international workshop on Language and Compilers for Parallel Computers, LNCS #1033, Columbus, Ohio, Aug. 1995.

    Google ScholarĀ 

  5. B. Dupont de Dinechin ā€œEfficient Computation of Margins and of Minimum Cumulative Register Lifetime Dateā€, Proceedings of 9th International Workshop on Language and Compilers for Parallel Computers, San Jose, California, Aug. 1996.

    Google ScholarĀ 

  6. M. Lam ā€œA Systolic Array Optimizing Compilerā€ Ph. D. Thesis, Carnegie Mellon University, May 1987.

    Google ScholarĀ 

  7. M. Lam ā€œSoftware Pipelining: An Effective Scheduling Technique for VLIW Machinesā€ Proceedings of the SIGPLAN'88 Conference on Programming Language Design and Implementation, 1988.

    Google ScholarĀ 

  8. B. R. Rau, C. D. Glaeser ā€œSome Scheduling Techniques and an Easily Schedulable Horizontal Architecture for High Performance Scientific Computingā€ IEEE / ACM 14th Annual Microprogramming Workshop, Oct. 1981.

    Google ScholarĀ 

  9. B. R. Rau ā€œIterative Modulo Scheduling: An Algorithm for Software Pipelining Loopsā€ IEEE / ACM 27th Annual Microprogramming Workshop, San Jose, California, Nov. 1994.

    Google ScholarĀ 

  10. B. R. Rau, M. S. Schlansker, P. P. Tirumalai ā€œCode Generation Schemas for Modulo Scheduled Loopsā€ MICRO-25 / 25th Annual International Symposium on Microarchitecture, Portland, Dec. 1992.

    Google ScholarĀ 

  11. J. Ruttenberg, G. R. Gao, A. Stoutchinin, W. Lichtenstein ā€œSoftware Pipelining Showdown: Optimal vs. Heuristic Methods in a Production Compilerā€ Proceedings of the SIGPLAN'96 Conference on Programming Language Design and Implementation, Philadelphia, May 1996.

    Google ScholarĀ 

  12. P. P. Tirumalai, M. S. Schlansker ā€œParallelization of Loops with Exits on Pipelined Architecturesā€ Proceedings of the Supercomputing'90 conference Nov. 1990.

    Google ScholarĀ 

  13. R. F. Touzeau ā€œA Fortran Compiler for the FPS-164 Scientific Computerā€ ACM SIGPLAN 84 Symposium on Compiler Construction, 1984.

    Google ScholarĀ 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Victor Malyshkin

Rights and permissions

Reprints and permissions

Copyright information

Ā© 1997 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Dupont de Dinechin, B. (1997). A unified software pipeline construction scheme for modulo scheduled loops. In: Malyshkin, V. (eds) Parallel Computing Technologies. PaCT 1997. Lecture Notes in Computer Science, vol 1277. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63371-5_20

Download citation

  • DOI: https://doi.org/10.1007/3-540-63371-5_20

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63371-6

  • Online ISBN: 978-3-540-69525-7

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics