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An adaptive parallel Genetic Algorithm for VLSI-layout optimization

  • Applications of Evolutionary Computation Evolutionary Computation in Electrical, Electronics, and Communications Engineering
  • Conference paper
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Parallel Problem Solving from Nature — PPSN IV (PPSN 1996)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1141))

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Abstract

The generation of a high quality layout during the design of a VLSI microchip is a very complex combinatorial optimization problem. Components of a circuit have to be placed, and signal nets have to be routed on an overall minimal area. In this paper a parallel Genetic Algorithm for the combined optimization of placement and routing is presented. The main focus is on the self-adaptation of the search process: Several islands execute a sequential GA with different strategies. At fixed intervals these strategies are ranked and each strategy is adjusted to the next better one by assimilating its characteristical parameters.

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Authors and Affiliations

  1. Dept. of Math./Computer Science, University of Osnabrück, D-49069, Osnabrück, Germany

    Volker Schnecke & Oliver Vornberger

Authors
  1. Volker Schnecke
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  2. Oliver Vornberger
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Editor information

Hans-Michael Voigt Werner Ebeling Ingo Rechenberg Hans-Paul Schwefel

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© 1996 Springer-Verlag Berlin Heidelberg

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Schnecke, V., Vornberger, O. (1996). An adaptive parallel Genetic Algorithm for VLSI-layout optimization. In: Voigt, HM., Ebeling, W., Rechenberg, I., Schwefel, HP. (eds) Parallel Problem Solving from Nature — PPSN IV. PPSN 1996. Lecture Notes in Computer Science, vol 1141. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61723-X_1049

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  • DOI: https://doi.org/10.1007/3-540-61723-X_1049

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-61723-5

  • Online ISBN: 978-3-540-70668-7

  • eBook Packages: Springer Book Archive

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