Abstract
The attractiveness of using theorem provers for system design verification lies in their generality. The major practical challenge confronting theorem proving technology is in combining this generality with an acceptable degree of automation. We describe an approach for enhancing the effectiveness of theorem provers for hardware verification through the use of efficient automatic procedures for rewriting, arithmetic and equality reasoning, and an off-the-shelf BDD-based propo-sitional simplifier. These automatic procedures can be combined into general-purpose proof strategies that can efficiently automate a number of proofs including those of hardware correctness. The inference procedures and proof strategies have been implemented in the PVS verification system. They are applied to several examples including an N-bit adder, the Saxe pipelined processor, and the benchmark Tamarack microprocessor design. These examples illustrate the basic design philosophy underlying PVS where powerful and efficient low-level inferences are employed within high-level user-defined proof strategies. This approach is contrasted with approaches based on tactics or batch-oriented theorem proving.
This work was supported in part by the following funding sources: NASA Langley Research Center contract NAS1-18969, ARPA Contract NAG2-891 administered by NASA Ames Research Center, NSF Grant CCR-930044, the Semiconductor Research Corporation contract 92-DJ-295 (to the University of British Columbia), and the Philips Research Laboratories, Eindhoven, The Netherlands.
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References
Mark D. Aagard, Miriam E. Leeser, and Phillip J. Windley. Toward a super duper hardware tactic. In Proceedings of the HOL User's Group Workshop, pages 401–414, 1993.
MartÃn Abadi and Leslie Lamport. The existence of refinement mappings. In Third Annual Symposium on Logic in Computer Science, pages 165–175. IEEE, Computer Society Press, July 1988.
R. J. Boulton. The HOL arith library. Technical report, University of Cambridge Computer Laboratory, 1992.
R. S. Boyer and J. S. Moore. A Computational Logic Handbook. Academic Press, New York, NY, 1988.
K. S. Brace, R. L. Rudell, and R. E. Bryant. Efficient implementation of a BDD package. In Proc. of the 27th ACM/IEEE Design Automation Conference, pages 40–45, 1990.
J. R. Burch and D. L. Dill. Automated verification of pipelined microprocessor control. In David Dill, editor, Computer-Aided Verification '94, pages 68–80. Volume 818 of Lecture Notes in Computer Science, Springer-Verlag, 1994.
F. J. Cantu. Verifying an n-bit arithmetic logic unit. Blue book note 935, University of Edinburgh, June 1994.
E. M. Clarke and O. Grümberg. Research on automatic verification of finite-state concurrent systems. In Joseph F. Traub, Barbara J. Grosz, Butler W. Lampson, and Nils J. Nilsson, editors, Annual Review of Computer Science, Volume 2, pages 269–290. Annual Reviews, Inc., Palo Alto, CA, 1987.
User Guide for the Ehdm Specification Language and Verification System, Version 6.1. Computer Science Laboratory, SRI International, Menlo Park, CA, February 1993. Three volumes.
D. Cyrluk and P. Narendran. Ground temporal logic-a logic for hardware verification. In David Dill, editor, Computer-Aided Verification '94, pages 247–259. Volume 818 of Lecture Notes in Computer Science, Springer-Verlag, 1994.
David Cyrluk. Microprocessor verification in PVS: A methodology and simple example. Technical Report SRI-CSL-93-12, SRI Computer Science Laboratory, December 1993.
P. J. Downey, R. Sethi, and R. E. Tarjan. Variations on the common subexpressions problem. Journal of the ACM, 27(4):758–771, October 1980.
M. J. C. Gordon and T. F. Melham, editors. Introduction to HOL: A Theorem Proving Environment for Higher-Order Logic. Cambridge University Press, Cambridge, UK, 1993.
Mike Gordon. Proving a computer correct. Technical Report TR 42, University of Cambridge, Computer Laboratory, 1983.
J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 1990.
Warren A. Hunt, Jr. Microprocessor design verification. Journal of Automated Reasoning, 5(4):429–460, December 1989.
G. Janssen. ROBDD Software. Department of Electrical Engineering, Eindhoven University of Technology, October 1993.
J. Joyce, G. Birtwistle, and M. Gordon. Proving a computer correct in higher order logic. Technical Report 100, Computer Lab., University of Cambridge, 1986.
R. Kumar, K. Schneider, and T. Kröpf. Structuring and automating hardware proofs in a higher-order therem proving environment. Formal Methods in System Design, 2(2):165–223, 1993.
Patrick Lincoln, Sam Owre, John Rushby, N. Shankar, and Friedrich von Henke. Eight papers on formal verification. Technical Report SRI-CSL-93-4, Computer Science Laboratory, SRI International, Menlo Park, CA, May 1993.
D. C. Luckham, S. M. German, F. W. von Henke, R. A. Karp, P. W. Milne, D. C. Oppen, W. Polak, and W. L. Scherlis. Stanford Pascal Verifier user manual. CSD Report STAN-CS-79-731, Stanford University, Stanford, CA, March 1979.
S. Owre, J. M. Rushby, and N. Shankar. PVS: A prototype verification system. In Deepak Kapur, editor, 11th International Conference on Automated Deduction (CADE), pages 748–752, Saratoga, NY, June 1992. Volume 607 of Lecture Notes in Artificial Intelligence, Springer-Verlag.
S. Owre, N. Shankar, and J. M. Rushby. User Guide for the PVS Specification and Verification System, Language, and Proof Checker (Beta Release). Computer Science Laboratory, SRI International, Menlo Park, CA, February 1993. Three volumes.
James B. Saxe, Stephen J. Garland, John V. Guttag, and James J. Horning. Using transformations and verification in circuit design. Formal Methods in System Design, 4(1):181–210, 1994.
N. Shankar. Abstract datatypes in PVS. Technical Report SRI-CSL-93-9, Computer Science Laboratory, SRI International, Menlo Park, CA, December 1993.
Robert E. Shostak. Deciding combinations of theories. Journal of the ACM, 31(1):1–12, January 1984.
Mandayam Srivas and Mark Bickford. Formal verification of a pipelined microprocessor. IEEE Software, 7(5):52–64, September 1990.
Mandayam Srivas and Steve Miller. Formal verification of the AAMP5 microprocessor: A case study in the industrial use of formal methods. Technical report. A Forthcoming NASA Contractor Report.
P. Windley and M. Coe. A correctness model for pipelined microprocessors. In Proceedings of Theorem Provers in Circuit Design, 1994.
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Cyrluk, D., Rajan, S., Shankar, N., Srivas, M.K. (1995). Effective theorem proving for hardware verification. In: Kumar, R., Kropf, T. (eds) Theorem Provers in Circuit Design. TPCD 1994. Lecture Notes in Computer Science, vol 901. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-59047-1_50
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