Abstract
The transaction ordering problem of the original PCI 2.1 standard bus specification violates the desired correctness property of maintaining the so called ‘Producer/Consumer’ relationship between writers and readers. In [3], a correction to this ordering problem was proposed and informally proved (called the “HP solution” here). In this paper, we present a formalization of the PCI 2.1 protocol in PVS. We formalize the fact that with Local Master ID added to the protocol no completion stealing is possible and the Producer/Consumer property is provided even in the presence of multiple readers. The state of our proofs leading to this result, as well as some of the much needed enhancements to theorem-proving frameworks that will greatly facilitate similar proofs, are also elaborated.
Supported in part by DARPA under contract #DABT6396C0094 (Utah Verifier), and NSF MIP MIP-9321836
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Ricky W. Butler and Jon A. Sjogren. A PVS Graph Theory Library. Technical Report Memorandum, NASA Langly Research Center, December1997. http://atb-www.larc.nasa.gov/ftp/larc/PVS-library.
E. M. Clarke, O. Grumberg, H. Hiraishi, S. Jha, D. E. Long, K. L. McMillan, and L. A. Ness. Verification of the futurebus+ cache coherence protocol. In L. Claeen, editor, Eleventh International Symposium on Computer Hardware Description Languages and their Applications. North-Holland, April 1993.
Francisco Corella. Verifying memory ordering model of I/O systems. In Invited talk at Computer Hardware Description Languages 1997, Toledo, Spain, April 1997.
Francisco Corella, Robert Shaw, and Cui Zhang. A formal proof of absence of deadlock for any acyclic network of PCI buses. In Computer Hardware Description Languages, 1997.
Rajnish Ghughal, Abdel Mokkedem, Ratan Nalumasu, and Ganesh Gopalakrishnan. Using ”test model-checking” to verify the runway-pa8000 memory model. In Tenth Annual ACM Symposium On Parallel Algorithms And Architectures, pages 231–239, Puerto Vallarta, Mexico, June 1998. ACM Press.
G. Gopalakrishnan, R. Ghughal, R. Hosabettu, A. Mokkedem, and R. Nalumasu. Formal modeling and validation applied to a commercial coherent bus: A case study. In Hon F. Li and David K. Probst, editors, CHARME, Montreal, Canada, 1997.
PCI Special Interest Group. PCI Local Bus Specification, Revision 2.1, June 1995.
A. Mokkedem. Verification of PCI 2.1 Local Bus in PVS. http://www.cs.utah.edu/~mokkedem/pvs/pvs.html.
Vijay Nagasamy, Sreeranga Rajan, and Preeti R. Panda. Fiber channel protocol: Formal specification and verification. In Sixth Annual Silicon Valley Networking Conference, 1997.
Ratan Nalumasu, Rajnish Ghughal, Abdel Mokkdem, and Ganesh Gopalakrishnan. The ‘test model-checking’ approach to the verification of formal memory models of multiprocessors. In Alan J. Hu and Moshe Y. Vardi, editors, Computer Aided Verification, volume 1427 of LNCS, pages 464–476, Vancouver, BC, Canada, June 1998. Springer-Verlag.
Sam Owre, John Rushby, Natarajan Shankar, and Friedrich von Henke. Formal verification for fault-tolerant architectures: Prolegomena to the design of PVS. IEEE Transactions on Software Engineering, 21(2):107–125, February 1995.
F. Corella. Hewlett Packard. Proposal to fix ordering problem in PCI 2.1, 1996. http://www.pcisig.com/reflector/thrd8.html#00706.
S. Park and D. L. Dill. Protocol verification by aggregation of distributed transactions. In Rajeev Alur and Thomas A. Henzinger, editors, Computer Aided Verification, volume 1102 of Lecture Notes in Computer Science, pages 300–309, New Brunswick, NJ, USA, July 1996. Springer-Verlag.
Edward Solari and George Willse. PCI Hardwarde and Software Architecture & Design. Annabooks, 3rd edition edition, December 1996. ISBN 0-929392-32-9.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1998 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Mokkedem, A., Hosabettu, R., Gopalakrishnan, G. (1998). Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem. In: Gopalakrishnan, G., Windley, P. (eds) Formal Methods in Computer-Aided Design. FMCAD 1998. Lecture Notes in Computer Science, vol 1522. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-49519-3_17
Download citation
DOI: https://doi.org/10.1007/3-540-49519-3_17
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-65191-8
Online ISBN: 978-3-540-49519-2
eBook Packages: Springer Book Archive