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Formalising UML State Machines for Model Checking

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«UML»’99 — The Unified Modeling Language (UML 1999)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1723))

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Abstract

The paper discusses a complete formalisation of UML state machine semantics. This formalisation is given in terms of an operational semantics and it can be used as the basis for code-generation, simulation and verification tools for UML Statecharts diagrams. The formalisation is done in two steps. First, the structure of a UML state machine is translated into a term rewriting system. In the second step, the operational semantics of state machines is defined. In addition, some problematic situations that may arise are discussed. Our formalisation is able to deal with all the features of UML state machines and it has been implemented in the vUML tool, a tool for model-checking UML models.

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Author information

Authors and Affiliations

  1. Turku Centre for Computer Science (TUCS), Lemminkäisenkatu 14 A, FIN-20520, Turku, Finland

    Johan Lilius & Iván Porres Paltor

Authors
  1. Johan Lilius
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  2. Iván Porres Paltor
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Editor information

Editors and Affiliations

  1. Department of Computer Science, Colorado State University, Fort Collins, CO, 80523-1873, USA

    Robert France

  2. Institut für Informatik, Technische Universität München, D-80290, München, Germany

    Bernhard Rumpe

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© 1999 Springer-Verlag Berlin Heidelberg

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Lilius, J., Paltor, I.P. (1999). Formalising UML State Machines for Model Checking. In: France, R., Rumpe, B. (eds) «UML»’99 — The Unified Modeling Language. UML 1999. Lecture Notes in Computer Science, vol 1723. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46852-8_31

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  • DOI: https://doi.org/10.1007/3-540-46852-8_31

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-66712-4

  • Online ISBN: 978-3-540-46852-3

  • eBook Packages: Springer Book Archive

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