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Design Tradeoffs for Embedded Network Processors

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Trends in Network and Pervasive Computing — ARCS 2002 (ARCS 2002)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2299))

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Abstract

Demands for flexible processing have moved general-purpose processing into the data path of networks. With the development of System-On-a-Chip technology, it is possible to put a number of processors with memory and I/O components on a single ASIC. We present a performance model of such a system and show how the number of processors, cache sizes, and the tradeoffs between the use of on-chip SRAM and DRAM can be optimized in terms of computation per unit chip area for a given workload. Based on a telecommunications benchmark the results of such an optimization are presented and design tradeoffs for Systems-on-a-Chip are identified and discussed.

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References

  1. ARM Ltd. ARM9E-S-Technical Reference Manual, Dec. 1999. http://www.arm.com.

  2. R. F. Cmelik and D. Keppel. Shade: A fast instruction-set simulator for execution profiling. In Proc. of ACM SIGMETRICS, Nashville, TN, May 1994.

    Google Scholar 

  3. P. Crowley, M. E. Fiuczynski, J.-L. Baer, and B. N. Bershad. Characterizing processor architectures for programmable network interfaces. In Proc. of 2000 International Conference on Supercomputing, Santa Fe, NM, May 2000.

    Google Scholar 

  4. J. Edler and M. D. Hill. Dinero IV Trace-Driven Uniprocessor Cache Simulator, 1998. http://www.neci.nj.nec.com/homepages/edler/d4/. 158

  5. IBM Microelectronics Division. The PowerPC 405TM Core, 1998. http://www.chips.ibm.com/products/powerpc/cores/405cr wp.pdf.

  6. MIPS Technologies, Inc. JADE-Embedded MIPS Processor Core, 1998. http://www.mips.com/products/Jade1030.pdf.

  7. T. Wolf and M. A. Franklin. CommBench— a telecommunications benchmark for network processors. In Proc. of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 154–162, Austin, TX,Apr. 2000.

    Google Scholar 

  8. T. Wolf and J. S. Turner. Design issues for high performance active routers. IEEE Journal on Selected Areas of Communication, 19(3):404–409, Mar. 2001.

    Article  Google Scholar 

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© 2002 Springer-Verlag Berlin Heidelberg

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Wolf, T., Franklin, M.A. (2002). Design Tradeoffs for Embedded Network Processors. In: Schmeck, H., Ungerer, T., Wolf, L. (eds) Trends in Network and Pervasive Computing — ARCS 2002. ARCS 2002. Lecture Notes in Computer Science, vol 2299. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45997-9_12

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  • DOI: https://doi.org/10.1007/3-540-45997-9_12

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-43409-2

  • Online ISBN: 978-3-540-45997-2

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