Abstract
In this paper we show how to translate bounded-length verification problems for timed automata into formulae in difference logic, a propositional logic enriched with timing constraints. We describe the principles of a satisfiability checker specialized for this logic that we have implemented and report some preliminary experimental results.
This work was partially supported by the EC project IST-2001-35302 AMETIST (Advanced Methods for Timed Systems).
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Niebert, P., Mahfoudh, M., Asarin, E., Bozga, M., Maler, O., Jain, N. (2002). Verification of Timed Automata via Satisfiability Checking. In: Damm, W., Olderog, E.R. (eds) Formal Techniques in Real-Time and Fault-Tolerant Systems. FTRTFT 2002. Lecture Notes in Computer Science, vol 2469. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45739-9_15
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