Abstract
Boolean circuits offer a natural, structured, and compact representation of Boolean functions for many application domains. In this paper a tableau method for solving satisfiability problems for Boolean circuits is devised. The method employs a direct cut rule combined with deterministic deduction rules. Simplification rules for circuits and a search heuristic attempting to minimize the search space are developed. Experiments in symbolic model checking domain indicate that the method is competitive against state-of-the-art satisfiability checking techniques and a promising basis for further work.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
A. Biere, A. Cimatti, E. Clarke, and Y. Zhu. Symbolic model checking without BDDs. In W. R. Cleaveland, editor, Tools and Algorithms for the Construction and Analysis of Systems (TACAS’99), volume 1579 of LNCS, pages 193–207. Springer, 1999.
A. Biere, A. Cimatti, E. M. Clarke, M. Fujita, and Y. Zhu. Symbolic model checking using SAT procedures instead of BDDs. In Proceedings of the 36th ACM/IEEE Design Automation Conference (DAC’99), pages 317–320. ACM, 1999.
A. Biere, E. Clarke, R. Raimi, and Y. Zhu. Verifying safety properties of a PowerPC microprocessor using symbolic model checking without BDDs. In N. Halbwachs and D. Peled, editors, Computer Aided Verification: 11th International Conference (CAV’99), volume 1633 of LNCS, pages 60–71. Springer, 1999.
A. Borälv. The industrial success of verification tools based on Stålmarck’s method. In Proceeding of the 9th International Conference on Computer Aided Verification (CAV’97), volume 1254 of LNCS, pages 7–10, Haifa, Israel, June 1997. Springer.
R. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, 35(8):677–691, 1986.
J. Burch, E. Clarke, K. McMillan, D. Dill, and L. Hwang. Symbolic model checking: 1020 states and beyond. Information and Computation, 98(2):142–170, 1992.
M. D’ Agostino and M. Mondadori. The taming of the cut. Journal of Logic and Computation, 4:285–319, 1994.
L. Guerra e Silva, L. M. Silveira, and J. Marques-Silva. Algorithms for solving Boolean satisfiability in combinatorial circuits. In Design, Automation and Test in Europe (DATE’99), pages 526–530. IEEE, 1999.
T. Junttila. BCSat — a satisfiability checker for Boolean circuits. Available at http://www.tcs.hut.fi/~tjunttil/bcsat.
H. Kautz, D. McAllester, and B. Selman. Exploiting variable dependency in local search. A draft available at http://www.cs.cornell.edu/home/selman/papers-ftp/papers.html, 1997.
H. Kautz and B. Selman. Pushing the envelope: Planning, propositional logic, and stochastic search. In Proceedings of the 13th National Conference on Artificial Intelligence, Portland, Oregon, July 1996.
C. Li and Anbulagan. Look-ahead versus look-back for satisfiability problems. In Principles and Practice of Constraint Programming-CP97, volume 1330 of LNCS, pages 341–355. Springer, 1997.
F. Massacci. Simplification — a general constraint propagation technique for propositional and modal tableaux. In H. de Swart, editor, Proceedings of the International Conference on Automated Reasoning with Analytic Tableaux and Related Methods (TABLEAUX-98), pages 217–231. Springer, May 1998.
A. Nerode and R. A. Shore. Logic for Applications. Text and Monographs in Computer Science. Springer-Verlag, 1993.
I. Niemelä and P. Simons. Efficient implementation of the well-founded and stable model semantics. In M. Maher, editor, Proceedings of the Joint International Conference and Symposium on Logic Programming, pages 289–303. The MIT Press, 1996.
C. H. Papadimitriou. Computational Complexity. Addison-Wesley, 1995.
R. Sebastiani. Applying GSAT to non-clausal formulas. Journal of Artificial Intelligence Research, 1:309–314, 1994.
P. Simons. Towards constraint satisfaction through logic programs and the stable model semantics. Research report A47, Helsinki University of Technology, Helsinki, Finland, August 1997. Available at http://www.tcs.hut.fi/pub/reports/A47.ps.gz.
H. Zhang. SATO: An efficient propositional prover. In Automated Deduction-CADE-14, volume 1249 of LNCS, pages 272–275. Springer, 1997.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2000 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Junttila, T.A., Niemelä, I. (2000). Towards an Efficient Tableau Method for Boolean Circuit Satisfiability Checking. In: Lloyd, J., et al. Computational Logic — CL 2000. CL 2000. Lecture Notes in Computer Science(), vol 1861. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44957-4_37
Download citation
DOI: https://doi.org/10.1007/3-540-44957-4_37
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-67797-0
Online ISBN: 978-3-540-44957-7
eBook Packages: Springer Book Archive