Skip to main content

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1896))

Included in the following conference series:

Abstract

Multitasking on an FPGA-based processor is one possibility to explore the efficacy of reconfigurable computing. Conventional computers and operating systems have demonstrated the many advantages of sharing computational hardware by several tasks over time. The ability to do run-time configuration and readback of FPGAs in a coprocessor architecture allows investigating the problems of implementing realistic multitasking. This paper explores the control software required to support task switching for an application split over the host processor — coprocessor boundary as well as the requirements and features of context saving and restoring in the FPGA coprocessor context. An FPGA coprocessor designed especially to support multitasking of such applications is described.

Work supported by the German-Israeli Foundation for Scientific Research and Development

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Mark Shand: PCI Pamette V1. DEC, Systems Research Center, Palo Alto, USA. 1997. http://www.research.digital.com/SRC/pamette

    Google Scholar 

  2. K.-H. Noffz and R. Lay: microEnable, Silicon Software GmbH, Mannheim, Germany. 1999. http://www.silicon-software.com

    Google Scholar 

  3. Virtual Computer Corporation: VCC H.O.T. II, Virtual Computer Corporation, Reseda, USA. 1997. http://www.vcc.com

    Google Scholar 

  4. R. Hudson, D. Lehn and P. Athanas: A Run-Time Reconfigurable Engine for Image Interpolation, IEEE Symposium on FPGAs for Custom Computing Machines, Los Alamitos, California. April 1998. Page 88–95.

    Google Scholar 

  5. G. Brebner: The Swappable Logic Unit: A Paradigm for Virtual Hardware, IEEE Symposium on FPGAs for Custom Computing Machines, Los Alamitos, California. April 1997. Pages 77–86.

    Google Scholar 

  6. J. Jean, K. Tomko, V. Yavagal, R. Cook and J. Shah: Dynamic Reconfiguration to Support Concurrent Applications, IEEE Symposium on FPGAs for Custom Computing Machines, Los Alamitos, California. April 1998. Pages 302–303.

    Google Scholar 

  7. H. Simmler, L. Levinson and R. Männer: Preemptive Multitasking on FPGAs. IEEE Symposium on FPGAs for Custom Computing Machines, Los Alamitos, California. April 2000. unpublished.

    Google Scholar 

  8. J. Nehmer and P. Sturm: Systemsoftware. dPunkt.Verlag. 1998.

    Google Scholar 

  9. Intel: Intel Architecture Software Developer’s Manual, Volume 3, Intel Inc.. 1999. http://www.intel.com/design/product.htm

  10. Xilinx Inc.: Virtex 2,5V Field Programmable Gate Arrays, Xilinx. San Jose, California 95124. 1999. http://www.xilinx.com/products/virtex.htm

    Google Scholar 

  11. IDT: Fast Static Rams and Modules, IDT Inc. 1999. http://www.idt.com/products/sram/Welcome.html

  12. Samsung: SRam Products, Samsung Semiconductor Inc.. 1999 http://www.usa.samsungsemi.com/products/browse/ntramsram.htm

  13. T. Kean and A. Duncan: DES Key Breaking, Encryption and Decryption on the XC6216, IEEE Symposium on FPGAs for Custom Computing Machines, Los Alamitos, California. April 1998. Pages 310–311.

    Google Scholar 

  14. H. Simmler, E. Bindewald, R. Männer: Acceleration of Protein Energy Calculation by FPGAs, Proc. Int’l Conf. on Mathematics and Engineering Techniques in Medicine and Biological Science. CSREA Press, June 2000. unpublished.

    Google Scholar 

  15. E. Bindewald, et.al.: Ab inition protein structure prediction with MOLEGO, Proc. 7th Int’l Conf. on Intelligent Systems for Molecular Biology. 1999.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2000 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Simmler, H., Levinson, L., Männer, R. (2000). Multitasking on FPGA Coprocessors. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_13

Download citation

  • DOI: https://doi.org/10.1007/3-540-44614-1_13

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67899-1

  • Online ISBN: 978-3-540-44614-9

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics