Abstract
The presented Triple-DES encryptor is a single-chip solution to encrypt network communication. It is optimized for throughput and fast switching between virtual connections like found in ATM networks. A broad range of optimization techniques were applied to reach encryption rates above 155 Mbps even for Triple-DES encryption in outer CBC mode. A high-speed logic style and full-custom design methodology made first-time working silicon on a standard 0.6μm CMOS process possible. Correct functionality of the prototype was verified up to a clock rate of 275 MHz.
The work described origins from the European Comission funded Project Secure Communications in ATM Networks (SCAN) established under contract AC0330 in the Advanced Communications Technologies and Services (ACTS)Program.
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Leitold, H., Mayerwieser, W., Payer, U., Posch, K.C., Posch, R., Wolkerstorfer, J. (2000). A 155 Mbps Triple-DES Network Encryptor. In: Koç, Ç.K., Paar, C. (eds) Cryptographic Hardware and Embedded Systems — CHES 2000. CHES 2000. Lecture Notes in Computer Science, vol 1965. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44499-8_12
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DOI: https://doi.org/10.1007/3-540-44499-8_12
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