Abstract
The main contribution of this paper is to present an FPGAbased implementation of an instance-specific hardware which accelerates the CKY (Cook-Kasami-Younger) parsing for context-free grammars. Given a context-free grammar G and a string x, the CKY parsing determines if G derives x. We have developed a hardware generator that creates a Verilog HDL source to perform the CKY parsing for any given context-free grammar G. The created source is embedded in an FPGA using the design software provided by the FPGA vendor. We evaluated the instance-specific hardware, generated by our hardware generator, using a timing analyzer and tested it using the Altera FPGAs. The generated hardware attains a speed-up factor of approximately 750 over the software CKY parsing algorithm. Hence, we believe that our approach is a promising solution for the CKY parsing.
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Bordim, J.L., Ito, Y., Nakano, K. (2002). Accelerating the CKY Parsing Using FPGAs. In: Sahni, S., Prasanna, V.K., Shukla, U. (eds) High Performance Computing — HiPC 2002. HiPC 2002. Lecture Notes in Computer Science, vol 2552. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36265-7_5
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DOI: https://doi.org/10.1007/3-540-36265-7_5
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