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Simulated Time for Testing Railway Interlockings with TTCN-3

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Formal Approaches to Software Testing (FATES 2005)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 3997))

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Abstract

Railway control systems are timed and safety-critical. Testing these systems is a key issue. Prior to system testing, the software of a railway control system is tested separately from the hardware. Here we show that real time and scaled time semantics are inefficient for testing this software. We provide a time semantics with simulated time and show that this semantics is more suitable for testing of software of railway control systems.

TTCN-3 is a standardized language for specifying and executing test suites. It supports real time and scaled time but not simulated time. We provide a solution that allows simulated time testing with TTCN-3. Our solution is based on Dijkstra’s distributed termination detection algorithm. The solution is implemented and can be reused for simulated time testing of other systems with similar characteristics.

This work is done within the project “TTMedal. Test and Testing Methodologies for Advanced Languages (TT-Medal)” [14].

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References

  1. Dijkstra, E.W., Feijen, W.H.J., Gasteren, A.J.M.v.: Derivation of a termination detection algorithm for distributed computations. Information Processing Letters 16(5), 217–219 (1983)

    Article  MathSciNet  MATH  Google Scholar 

  2. ETSI ES 201 873-1 V2.2.1 (2003-02). Methods for Testing and Specification (MTS); The Testing and Test Control Notation version 3; Part 1: TTCN-3 Core Language. ETSI Standard

    Google Scholar 

  3. ETSI ES 201 873-4 V2.2.1 (2003-02). Methods for Testing and Specification (MTS); The Testing and Test Control Notation version 3; Part 4: TTCN-3 Operational Semantics. ETSI Standard

    Google Scholar 

  4. ETSI ES 201 873-5 V1.1.1 (2003-02). Methods for Testing and Specification (MTS); The Testing and Test Control Notation version 3; Part 5: TTCN-3 Runtime Interface (TRI). ETSI Standard

    Google Scholar 

  5. ETSI ES 201 873-6 V1.1.1 (2003-02). Methods for Testing and Specification (MTS); The Testing and Test Control Notation version 3; Part 6: TTCN-3 Control Interface (TCI). ETSI Standard

    Google Scholar 

  6. Fokkink, W.J.: Safety criteria for the vital processor interlocking at hoorn-kersenboogerd. In: Allan, J., Brebbia, C.A., Hill, R.J., Sciutto, G., Sone, S. (eds.) Proc. 5th Conference on Computers in Railways - COMPRAIL 1996, Railway Systems and Management, Computational Mechanics, Berlin, vol. I, pp. 101–110 (1996)

    Google Scholar 

  7. Gnesi, S., Latella, D., Lenzini, G., Abbaneo, C., Amendola, A.M., Marmo, P.: An automatic spin validation of a safety critical railway control system. In: DSN 2000: Proceedings of the 2000 International Conference on Dependable Systems and Networks (formerly FTCS-30 and DCCA-8), pp. 119–124. IEEE Computer Society, Los Alamitos (2000)

    Google Scholar 

  8. Grabowski, J., Hogrefe, D., Réthy, G., Schieferdecker, I., Wiles, A., Willcock, C.: An introduction into the testing and test control notation (TTCN-3). Computer Networks 42(3), 375–403 (2003)

    Article  MATH  Google Scholar 

  9. Haxthausen, A.E., Peleska, J.: Automatic verification, validation and test for railway control systems based on domain-specific descriptions

    Google Scholar 

  10. Henzinger, T.A., Manna, Z., Pnueli, A.: What good are digital clocks? In: Kuich, W. (ed.) ICALP 1992. LNCS, vol. 623, pp. 545–558. Springer, Heidelberg (1992)

    Chapter  Google Scholar 

  11. Marscheck, U.: Elektronische Stellwerke-internationale Überblick. SIGNAL+DRAHT 89 (1997)

    Google Scholar 

  12. Nicollin, X., Sifakis, J.: An overview and synthesis on timed process algebras. In: Proc. of the Real-Time: Theory in Practice, REX Workshop, pp. 526–548. Springer, Heidelberg (1992)

    Chapter  Google Scholar 

  13. <testing_tech> Testing Technologies, http://www.testingtech.de

  14. TTMedal. Testing and Testing Methodologies for Advanced Languages, http://www.tt-medal.org

  15. van Dijk, F.J., Fokkink, W.J., Kolk, G.P., van de Ven, P.H.J., van Vlijmen, S.F.M.: Euris, a specification method for distributed interlockings. In: Ehrenberger, W. (ed.) SAFECOMP 1998. LNCS, vol. 1516, pp. 296–305. Springer, Heidelberg (1998)

    Chapter  Google Scholar 

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Blom, S., Ioustinova, N., van de Pol, J., Rennoch, A., Sidorova, N. (2006). Simulated Time for Testing Railway Interlockings with TTCN-3. In: Grieskamp, W., Weise, C. (eds) Formal Approaches to Software Testing. FATES 2005. Lecture Notes in Computer Science, vol 3997. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11759744_1

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  • DOI: https://doi.org/10.1007/11759744_1

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-34454-4

  • Online ISBN: 978-3-540-34455-1

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