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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3855))

Abstract

We consider the problem of synthesizing digital designs from their ltl specification. In spite of the theoretical double exponential lower bound for the general case, we show that for many expressive specifications of hardware designs the problem can be solved in time N 3, where N is the size of the state space of the design. We describe the context of the problem, as part of the Prosyd European Project which aims to provide a property-based development flow for hardware designs. Within this project, synthesis plays an important role, first in order to check whether a given specification is realizable, and then for synthesizing part of the developed system.

This research was supported in part by the Israel Science Foundation (grant no.106/02-1), European community project Prosyd, the John von-Neumann Minerva center for Verification of Reactive Systems, NSF grant CCR-0205571, ONR grant N00014-99-1-0131, and SRC grant 2004-TJ-1256.

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Piterman, N., Pnueli, A., Sa’ar, Y. (2005). Synthesis of Reactive(1) Designs. In: Emerson, E.A., Namjoshi, K.S. (eds) Verification, Model Checking, and Abstract Interpretation. VMCAI 2006. Lecture Notes in Computer Science, vol 3855. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11609773_24

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  • DOI: https://doi.org/10.1007/11609773_24

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-31139-3

  • Online ISBN: 978-3-540-31622-0

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