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Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation

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Principles and Practice of Constraint Programming - CP 2005 (CP 2005)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 3709))

Abstract

This paper describes an efficient, complete approach for solving a complex allocation and scheduling problem for Multi-Processor System-on-Chip (MPSoC). Given a throughput constraint for a target application characterized as a task graph annotated with computation, communication and storage requirements, we compute an allocation and schedule which minimizes communication cost first, and then the makespan given the minimal communication cost. Our approach is based on problem decomposition where the allocation is solved through an Integer Programming solver, while the scheduling through a Constraint Programming solver. The two solvers are interleaved and their interaction regulated by no-good generation. Experimental results show speedups of orders of magnitude w.r.t. pure IP and CP solution strategies.

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References

  1. Wolf, W.: The future of multiprocessor systems-on-chips. In: Procs. of the 41st Design and Automation Conference - DAC 2004, San Diego, CA, USA, pp. 681–685. ACM Press, New York (2004)

    Chapter  Google Scholar 

  2. Benders, J.F.: Partitioning procedures for solving mixed-variables programming problems. Numerische Mathematik 4, 238–252 (1962)

    Article  MathSciNet  MATH  Google Scholar 

  3. Hooker, J.N.: A hybrid method for planning and scheduling. In: Wallace, M. (ed.) CP 2004. LNCS, vol. 3258, pp. 305–316. Springer, Heidelberg (2004)

    Chapter  Google Scholar 

  4. Grossmann, I.E., Jain, V.: Algorithms for hybrid milp/cp models for a class of optimization problems. INFORMS Journal on Computing 13, 258–276 (2001)

    Article  MathSciNet  Google Scholar 

  5. Culler, D.A., Singh, J.P.: Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann, San Francisco (1999)

    Google Scholar 

  6. Compton, K., Hauck, S.: Reconfigurable computing: A survey of systems and software. ACM Computing Surveys 34, 171–210 (1999)

    Article  Google Scholar 

  7. Hooker, J.N.: Planning and scheduling by logic-based benders decomposition. Technical report (2004), http://web.tepper.cmu.edu/jnh/planning.pdf

  8. Prakash, S., Parker, A.: Sos: Synthesis of application-specific heterogeneous multiprocessor systems. Journal of Parallel and Distributed Computing 16, 338–351 (1992)

    Article  MATH  Google Scholar 

  9. Lee, C., Potkonjak, M., Wolf, W.: System-level synthesis of application-specific systems using A* search and generalized force-directed heuristics, San Diego, California, pp. 2–7 (1996)

    Google Scholar 

  10. Bender, A.: Milp based task mapping for heterogeneous multiprocessor systems. In: EURO-DAC 1996/EURO-VHDL 1996: Procs. of the conference on European design automation, Geneva, Switzerland, pp. 190–197. IEEE, Los Alamitos (1996)

    Chapter  Google Scholar 

  11. Li, Y., Wolf, W.H.: Hardware/software co-synthesis with memory hierarchies 18, 1405–1417 (1999)

    Google Scholar 

  12. Meftali, S., Gharsalli, F., Jerraya, A.A., Rousseau, F.: An optimal memory allocation for application-specific multiprocessor system-on-chip. In: Proceedings of the 14th international symposium on Systems synthesis - ISSS 2001, pp. 19–24. ACM Press, New York (2001)

    Chapter  Google Scholar 

  13. De Micheli, G.: Synthesis and optimization of digital circuits. McGraw-Hill, New York (1994)

    Google Scholar 

  14. Chatha, K.S., Vemuri, R.: Hardware-software partitioning and pipelined scheduling of transformative applications 10, 193–208 (2002)

    Google Scholar 

  15. Fohler, G., Ramamritham, K.: Static scheduling of pipelined periodic tasks in distributed real-time systems. In: Procs. of the 9th EUROMICRO Workshop on Real-Time Systems - EUROMICRO-RTS 1997, Toledo, Spain, pp. 128–135. IEEE, Los Alamitos (1997)

    Chapter  Google Scholar 

  16. Palazzari, P., Baldini, L., Coli, M.: Synthesis of pipelined systems for the contemporaneous execution of periodic and aperiodic tasks with hard real-time constraints. In: 18th International Parallel and Distributed Processing Symposium - IPDPS 2004, pp. 121–128 (2004)

    Google Scholar 

  17. Bakshi, S., Gajski, D.D.: A scheduling and pipelining algorithm for hardware/software systems. In: Proceedings of the 10th international symposium on System synthesis - ISSS 1997, Washington, DC, USA, pp. 113–118. IEEE Computer Society, Los Alamitos (1997)

    Chapter  Google Scholar 

  18. Axelsson, J.: Architecture synthesis and partitioning of real-time synthesis: a comparison of 3 heuristic search strategies. In: Procs. of the 5th Intern. Workshop on Hardware/Software Codesign (CODES/CASHE 1997), Braunschweig, Germany, pp. 161–166. IEEE, Los Alamitos (1997)

    Chapter  Google Scholar 

  19. Eles, P., Peng, Z., Kuchcinski, K., Doboli, A.: System level hardware/software partitioning based on simulated annealing and tabu search. Design Automation for Embedded Systems 2, 5–32 (1997)

    Article  Google Scholar 

  20. Kodase, S., Wang, S., Gu, Z., Shin, K.: Improving scalability of task allocation and scheduling in large distributed real-time systems using shared buffers. In: Procs. of the 9th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2003), Toronto, Canada, pp. 181–188. IEEE, Los Alamitos (2003)

    Chapter  Google Scholar 

  21. Eles, P., Peng, Z., Kuchcinski, K., Doboli, A., Pop, P.: Scheduling of conditional process graphs for the synthesis of embedded systems, Paris, France, pp. 132–139 (1998)

    Google Scholar 

  22. Kuchcinski, K., Szymanek, R.: A constructive algorithm for memory-aware task assignment and scheduling. In: Procs of the Ninth International Symposium on Hardware/Software Codesign - CODES 2001, Copenhagen, Denmark, pp. 147–152. ACM Press, New York (2001)

    Google Scholar 

  23. Kuchcinski, K.: Embedded system synthesis by timing constraint solving. IEEE Transactions on CAD 13, 537–551 (1994)

    Google Scholar 

  24. Milano, M.: Constraint and Integer Programming: toward a unified methodolody. Kluwer Academic Publishers, Dordrecht (2004)

    Google Scholar 

  25. Hooker, J.N., Yan, H.: Logic circuit verification by benders decomposition. In: Principles and Practice of Constraint Programming: The Newport Papers, Cambridge, MA, pp. 267–288. MIT Press, Cambridge (1995)

    Google Scholar 

  26. Eremin, A., Wallace, M.: Hybrid benders decomposition algorithms in constraint logic programming. In: Walsh, T. (ed.) CP 2001. LNCS, vol. 2239, pp. 1–15. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  27. Cambazard, H., Déplanche, A.M., Hladik, P.E., Jussien, N., Trinquet, Y.: Decomposition and learning for a hard real time task allocation problem. In: Wallace, M. (ed.) CP 2004. LNCS, vol. 3258, pp. 153–167. Springer, Heidelberg (2004)

    Chapter  Google Scholar 

  28. Thorsteinsson, E.S.: A hybrid framework integrating mixed integer programming and constraint programming, Paphos, Cyprus, pp. 16–30 (2001)

    Google Scholar 

  29. Hooker, J.N., Ottosson, G.: Logic-based benders decomposition. Mathematical Programming 96, 33–60 (2003)

    MathSciNet  MATH  Google Scholar 

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Benini, L., Bertozzi, D., Guerri, A., Milano, M. (2005). Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation. In: van Beek, P. (eds) Principles and Practice of Constraint Programming - CP 2005. CP 2005. Lecture Notes in Computer Science, vol 3709. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11564751_11

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  • DOI: https://doi.org/10.1007/11564751_11

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-29238-8

  • Online ISBN: 978-3-540-32050-0

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