Abstract
We describe a fragment of the hardware description language VHDL that is suitable for implementing the Advanced Encryption Standard algorithm. We then define an Information Flow analysis as required by the international standard Common Criteria. The goal of the analysis is to identify the entire information flow through the VHDL program. The result of the analysis is presented as a non-transitive directed graph that connects those nodes (representing either variables or signals) where an information flow might occur. We compare our approach to that of Kemmerer and conclude that our approach yields more precise results.
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Tolstrup, T.K., Nielson, F., Nielson, H.R. (2005). Information Flow Analysis for VHDL. In: Malyshkin, V. (eds) Parallel Computing Technologies. PaCT 2005. Lecture Notes in Computer Science, vol 3606. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11535294_8
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DOI: https://doi.org/10.1007/11535294_8
Publisher Name: Springer, Berlin, Heidelberg
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