Comparison of annealing quality after 3e15/cm2 50 keV BF2+ implant between rapid thermal annealing and furnace annealing

Low leakage diodes are necessary in order to manufacture high-quality variable capacitance diodes (varicaps), which are used in voltage-controlled oscillators. Junction leakage current affects the single sideband noise of the oscillator by up-conversion of 1/f and shot noise (Chan et al. in IEEE Trans Electron Devices 54(9):2570–2573, 2007, https://doi.org/10.1109/TED.2007.903201). Several sources show higher leakage current for RTP compared to furnace anneal (Lunnon et al. in J Electrochem Soc 132(10):2473, 1985, https://doi.org/10.1149/1.2113602, Gramenova et al. in J Electrochem Soc 146(1):359, 1999, https://doi.org/10.1149/1.1391613, Mikoshiba et al. in Jpn J Appl Phys, 1986, https://doi.org/10.1143/jjap.25.l631). In our experiments, we found lower leakage currents for RTP compared to furnace annealing. We present results from annealing experiments where we compare three annealing conditions with and without oxidizing annealing conditions.


Introduction and motivation
Phase noise, mostly expressed as single-sideband noise, is one of the most important figures of merit for oscillators. A well-known formula to express phase noise is the Leeson equation, Eq. 1. Close to the carrier frequency, f 0 , the flicker noise of the transistor determined by f c and the diode leakage current's shot noise dominate [1]. Both noise sources contribute to the single sideband noise by up-conversion of the 1/f and shot noise [2]. In order to minimize the diode's shot noise contribution, the leakage current has to be minimized. A deeper analysis of the noise contribution of diodes in variable capacitance oscillators (VCOs) is given in [3].
We compare the leakage current of pn diodes annealed at 1000 °C using RTP and furnace annealing with different annealing times. Leakage current contributions are extracted using a simple area and perimeter contribution model. Furthermore, high-resolution TEM and process simulation were performed to explain the experimental findings.

Materials and methods
We used 200-mm n-type silicon epi-wafers, 0.02 Ωcm bulk resistivity, with an epitaxially grown, 1 × 10 15 cm −3 phosphorus-doped layer serving as cathode. The anode was defined by a thermally grown, wet-etched oxide hard-mask as shown in Fig. 1a. The anode doping was made by implanting BF2 at 50 keV with a dose of 3 × 10 15 cm −2 through 25-nm screen oxide using a Varian E500 implanter. The annealing temperature of 1000 °C was equal for all atmospheric conditions and tools. For furnace annealing, a TS series horizontal furnace of Tempress was used. For the RTP annealing, an atmospheric Mattson RTP, SHS 2800, was used. To avoid any oxygen residuals (≪ 1 ppm), the RTP was purged with pure nitrogen for 10 min before annealing to assure a pure nitrogen ambient during annealing. For the furnace annealing for all atmospheric conditions, a constant gas flow was chosen. Standby temperature of the tube was 600 °C.

Electrical characterization
As a demonstration vehicle, we fabricated circular-shaped pn-diodes with varying diameters from 75 to 300 µm to distinguish between area and edge contributions of the leakage current measured at 5-V reverse bias. Furthermore, all diodes are designed with a p+ guard ring to suppress diffusion leakage currents as depicted in Fig. 1a.

Results
The annealing conditions to identify the effect on the leakage of the diodes are listed below. An overview of the normalized measured leakage current at 5 V reverse bias of diodes with a diameter of 250 µm is shown in Fig. 1b. In order to extract edge and area leakage current densities, we used a simple model as shown in Eq. 2.
With I leak the measured leakage current at 5 V reverse bias, r the radius of the diode, a the edge contribution parameter, and b the area contribution parameter.
By normalizing I leak to the area of the diode, Eq. 3 yields a current density I leak norm with a 1 = a/(2π) and b 1 = b/(2π). In Fig. 1b, the measured current densities, I leak norm , at 5 V reverse bias of diodes with varying radii in the center of the wafers are shown. The slope of the curve corresponds to a 1 and the offset is b 1 . The data for Fig. 1a were obtained from devices in the center of the wafers. Furthermore, the leakage current at 5 V reverse bias was measured for diodes with 250 µm diameter at 49 points homogenously distributed over the wafer for all conditions. The values obtained from the analysis are: As shown above and in Fig. 1b, the area and the perimeter leakage current densities are the lowest for RTP annealing under a pure nitrogen atmosphere. Nearly a factor of 10 more for a 1 , the perimeter current density, is derived for furnace annealing. The area current density b 1 is bigger by a factor of more than 2. A discussion on possible reasons for the lower leakage current RTP-annealed samples follows in the simulation section below.

TEM analysis
TEM analysis was performed as a planar view and crosssectional TEM to enhance the understanding of the contribution to the leakage current. The planar views investigated showed dislocation networks for RTP and furnace annealing. The planar view of sample 2 is shown in Fig. 2b. The cross-sectional view in Fig. 2a shows a high concentration of dislocations near the silicon surface due to the high dose implant and subsequent annealing [4] for Sample 2. However, as the marking of the pn-junction shows, these . 1 a Cross-section schematics of the diodes used for experiments, diode diameter was varied in different experiments, b measured leakage current density as a function of inverse radius 1/r for several annealing conditions and diameters of the diodes at 5 V bias voltage dislocation networks are far away from the electrically active junction and therefore should have no to little influence on the area leakage current density. For a furnace anneal with prolonged diffusion during ramp-up and ramp-down, the junction is even farther away from the defects.

Process simulation
The process simulations, which calculated the evolution of extended defects, including 311 linear defects and dislocation loops, during thermal annealing, have been carried out using the Sentaurus Process software of Synopsys with Advanced Calibration [5]. The model for the evolution of dislocation loops was extended according to the work of Wolf et al. [6]. It was implemented and verified at IISB using the Alagator language of Sentaurus Process version S-2021.06. The following annealing conditions were simulated: 20-min RTP and 20-min furnace. The temperature profiles simulated also included ramping-up and rampingdown phases. The up and down ramping times in RTP were equal each of 5 s, in furnace annealing the ramping-up lasted 30 min and the ramping down 45 min.

Results
Since the analysis of the experimental data on leakage currents obtained for varying diode radii under variable annealing conditions showed the biggest difference for the leakage current density at the edges of the cathode electrodes, we simulated 2D distribution of doping and of defect densities near the cathode edges. The simulated distribution of the net-doping near the cathode edge after a furnace annealing for 20 min at 1000 °C is shown in Fig. 3a. Negative values of the net-doping mean p-type doping and positive values n-type doping. The depth of the pn-junction amounts to 0.8 µm, and the junction penetration under the oxide mask edge is 0.6 µm. In Fig. 3b, the distribution of silicon interstitials that were incorporated into the dislocation loops that were built during furnace annealing under same conditions is shown. It should be noted that according to the simulation model, faulted dislocations are the dominating type of dislocations for the annealing conditions considered in this paper. The presence of dislocation-incorporated interstitials means the presence of dislocation loops of different sizes at the same locations. If we consider the isolines of the incorporated silicon interstitials, we observe that some isolines cross the pn-junction at the edge of the p-type doping distribution. The same isolines remain inside of the p-doped area in the flat part of the cathode doping at the left side of Fig. 3b. Such a penetration of the defect isolines through a pn-junction can indicate a potential enhancement of the leakage current density at the edges of the cathode doping areas. Of course, this statement implies the fact that the dislocation loops that cross pn-junction enhance the leakage current [7][8][9]. In Fig. 4, the time evolution of the silicon atom sheet concentration incorporated into dislocation loops and the dislocation loop sheet concentration for both annealing conditions are presented for the flat part of the cathode doping at the left side of Fig. 3b. A higher sheet concentration of silicon atoms incorporated into dislocation loops leads to a higher mean loop radius for a constant loop concentration. An increase of the radius as well as an increase in density of the dislocation loops enhances the probability of the leakage current enhancement. Figure 3a shows the simulated time evolution of the mean sheet density of the interstitials incorporated in dislocation loops and sheet density of faulted loops for the 20-min RTP annealing in N2 atmosphere. The insert in Fig. 4 shows the same with a finer time resolution for the first 20 s of RTP annealing. We see that the maximum of the dislocation loop density is achieved already at 5 s of annealing, 1 s after reaching the maximum temperature of 1000 °C. During the rest of the annealing duration, only a reduction of the dislocation loop density happens as a result of the annealing. The same trends hold for furnace annealing, but due to the lower temperature slope during ramp-up, higher dislocation density is built during the ramp-up stage. Even a longer ramp-down time cannot reduce the dislocation loop density in furnace annealing to the low level of the of RTP annealing as can be seen in Fig. 4b. The reduction of the concentration of dislocation loops in case of RTP annealing compared to furnace annealing is due to a faster transition to temperatures over 950 °C at which the annealing process of the dislocation loops begins, as shown in Fig. 4b [6]. The mean radius for dislocations reaches a 35 nm for 20-min RTP, while it settles at 42 nm for furnace annealing.
The simulated concentration of dislocation loops reaches a value of approximately 1 × 10 9 /cm 2 for both annealing conditions at the end of annealing. The average dislocation loop size for RTP annealing is 35 nm and 42 nm for furnace annealing. The distance between the centers of the dislocation loops, (1/√DFLoop), is approximately 300 nm. Taking the sizes of the dislocation loops into account, this results in an average distance between dislocation loops of 265 nm for RTP annealing and 258 nm for furnace annealing. We speculate that the distance between the dislocation loops has an impact on the leakage current. Minority carriers might hop from one dislocation loop to another. Therefore, a reduced distance between dislocation loops might lead to higher leakage currents.

Conclusion
The results of the leakage current measurement obtained from pn-diodes show that RTA results in lower leakage current compared to furnace annealing. This stands in contrast to observations in literature [10][11][12][13]. In accordance with simulation results, the experiments can be explained qualitatively by the formation of dislocation loops and their capture of silicon self-interstitials depending on time and annealing temperature. The enhancement of the leakage current at the edge of the anode doping area is due to a presence of dislocation loops near pn-junction at the side edge of the doping area. The shorter ramp-up phase for RTP annealing reduces the concentration of silicon atoms incorporated into dislocation loops compared to furnace annealing. A comparison of the simulated dislocation loops parameters with the measurements of TEM indicates that simulation underestimates the density of dislocation loops and that the shape of the observed dislocation loops is more complicated Fig. 4 a Total number of dislocation loops (DFLoop) and total number of silicon atoms in dislocation loops (CFLoop) over time for RTP annealing, b for furnace annealing. Insert: excerpt of first 20 s, marked by red lines in top than the disc-like shape assumed in simulations. The type of simulated dislocation loop differs from the ones observed in planar view TEM. However, the type of dislocation loop should not have an influence on the leakage current. The trends predicted by the simulation are in qualitative agreement with the measurements.