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Modeling Silicon Cylindrical CMOS Nanotransistors with a Fully Enclosed Variable-Radius Gate

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Abstract

A new silicon CMOS nanotransistor with a cylindrical geometry of a fully enclosed variable-radius gate is discussed. A 2-D analytical model of the potential distribution and models of direct and subthreshold currents of a transistor with a truncated cone-shaped operating region based on it are developed. Changing the geometry of the transistor from the usual cylindrical shape improves the electrical-physical characteristics and allows us to compensate the limitations resulting from scaling. Numerical studies of conical prototypes demonstrate improved electrostatic performance at an optimized radius ratio of 0.83 compared to a conventional cylindrical structure in the control voltage range from 0 to 0.6 V. The conical structure features a higher transistor current, maximum current ratio Ion/Ioff, low leakage current, and the slope of the subthreshold characteristic close to the theoretical limit. Thus, a conical architecture with an optimized radius ratio can replace a cylindrical structure for high-speed and low-voltage applications.

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Funding

This study is part of a state task of the Scientific Research Institute for System Analysis, Russian Academy of Sciences “Conducting fundamental scientific research (47 GP)” on topic no. FNEF-2021-0001 “Mathematical support and tools for modeling, designing, and developing elements of complex technical systems, software systems, and telecommunication networks in various problem-oriented regions (0580-2021-0001)” reg. no. 121031300047-6.

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  1. Scientific Research Institute for System Analysis, Russian Academy of Sciences, Moscow, Russia

    N. V. Masalsky

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  1. N. V. Masalsky
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Correspondence to N. V. Masalsky.

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Masalsky, N.V. Modeling Silicon Cylindrical CMOS Nanotransistors with a Fully Enclosed Variable-Radius Gate. Russ Microelectron 51, 220–225 (2022). https://doi.org/10.1134/S1063739722040084

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  • DOI: https://doi.org/10.1134/S1063739722040084

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