A modular switched-capacitor multilevel inverter featuring voltage gain ability

This article presents a modular switched-capacitor multilevel inverter which uses two capacitors and a single dc source to obtain triple voltage gain. It is worth noting that the inherent inversion capacity removes the H-bridge, which can efficaciously diminish the voltage stress of switches, and the maximum voltage stress (MVS) on devices is kept within 2Vdc. Additionally, the proposed topology is able to integrate inductive load, and the capacitor voltage self-balancing can be achieved. Moreover, the modular structure also has an expandable topology which can generate more levels and raise the voltage gain by using multiple switched-capacitor units, meanwhile the voltage stress on power switches can be kept within 2Vdc. Furthermore, comprehensive analysis and comparison with other multilevel inverters have been implemented to certify the superiority of the proposed topology. Finally, the steady-state and dynamic performance of the proposed topology is examined through a seven-level inverter prototype, the validity and practicability of the topology are verified by simulations and experiments.


Introduction
To achieve net-zero carbon emission, the use of renewable energy like solar energy and wind energy is increasing.The conversion of DC to AC is an important interface for the photovoltaic power generation system.The DC voltage produced by the panels is low, which needs an inverter with a voltage boosting capability to meet the applications of medium voltage systems.
Multilevel inverters (MLIs), which are composed of power switches, capacitors and other components, can generate multiple voltage levels with low total harmonic distortion and also play a crucial role in energy conversion systems including photovoltaic power generation [1][2][3].Conventional MLIs can be divided into three types: diodeclamped multilevel inverter [4,5], flying capacitor multilevel inverter [6,7] and cascaded H-bridge multilevel inverter [8,9].However, the diode-clamped MLIs employ a lot of clamping diodes to obtain multilevel output, and the flying capacitor MLIs need numerous clamping capacitors which need a complex control strategy to achieve the voltage-selfbalance.Cascaded H-bridge MLIs can obtain multilevel voltage by utilizing multiple isolated sources, which leads to an increase in cost and limits the application scenarios.It is noteworthy that the modular multilevel converters have come to be emerging multilevel voltage converter topology due to their modularity and superb performance.However, the capacitor voltage balancing strategies are complex [10].
To overcome the gaps of the above-mentioned converters, the switched-capacitor multilevel inverters (SCMLIs) have been the popular method, which has the advantages of reducing the dv/dt on switches, voltage-self-balance, low switching frequency, and so on [11,12].The SCMLIs can obtain voltage gain using a switched-capacitor technique, and the polarity of the output voltage can be changed through the H-bridge structure [13][14][15].The switched-capacitor inverter proposed in [13] can achieve seven-level output, which uses fewer power devices than the traditional multilevel inverter and reduces the voltage fluctuation of the capacitor.The work [15] also proposes a 7-level inverter with self-voltage balancing, which can integrate inductive loads.However, the above SCMLIs only output a limited number of levels and achieve a low boosting factor.Some expandable SCM-LIs with H-bridge are proposed successively [16][17][18].The expandable SCMLIs with two different topologies are proposed in [17].The inverter can be extended by employing n units to increase boosting factor.A new inverter topology structure is proposed based on switched capacitor (SC) cell in [18], which can be expanded to obtain more output levels and the capacitor voltage is self-balanced as well.
The above designs have a common demerit of using an H-bridge to change voltage polarity, which leads to power switches sustain the crest value of output voltage.Therefore, the switched-capacitor inverter proposed in [19] can output seven-level without H-bridge, and maximum voltage stress is kept within 2V dc which can efficaciously lower the total standing voltage (TSV).Furthermore, a nine-level SCMLI is proposed in [20].The inverter can make sure that the peak reverse voltage of switches is kept within V dc , and a voltage gain of 2 is obtained.With the development of research, expandable multilevel inverters without H-bridge have been proposed [21,22].The topology proposed in [21] has a novel structure of switched-capacitor, and numerous voltage levels can be obtained to improve the boosting factor.However, the maximum voltage stress of power switches is the peak of output voltage.The switched-capacitor inverter proposed in [22] can boost input voltage with reduced power switches, and the voltage of all capacitors is self-balanced without using other circuits.The topology removed H-bridge because of the inherent polarity generation circuit since the voltage stress is also reduced.
The H-bridge is replaced by two half-bridges on both sides of the inverters to diminish the stress on switches [23][24][25].The inverter proposed in [23] set an appropriate ratio of dc sources to significantly increase the output levels.However, the stress of some switches also is the maximum value of output voltage, the same issue can be found in [24].The inverter proposed in [25] has low voltage stress on switches, but numerous devices are employed to reduce voltage stress.
In this study, a 7-level modular switched-capacitor inverter is proposed, the topology can obtain triple voltage gain with two capacitors.Additionally, the maximum voltage stress (MVS) of switches is kept within 2V dc , and the inverter can achieve the inversion process without H-bridge.Moreover, the capacitor voltage can be self-balanced which simplifies the control strategy.Based on the above analysis, a comprehensive comparison has been carried out, which is summarized in Table 1.

Configuration and operation principle
In this section, the working principle of the switched-capacitor is given following the introduction of the topology.On this basis, a bidirectional switched-capacitor module is submitted.Then the proposed SCMLI is formed through the combination of the modules.

Switched-capacitor module
To reduce the stress on switches and obtain the boosting factor, Fig. 1a shows a bidirectional switched-capacitor module of the proposed topology.The switched-capacitor module is presented in the shadow square.It can be seen

The gaps of previous topologies
The method of proposed topology High MVS of switches: in topologies [13,14,18] The MVS of all switches is kept within 2V dc Multiple dc sources are employed: in topologies [16,23,24] Single dc source is used Low voltage gain: in topologies [11,19,20] A triple voltage gain is obtained Complex control of capacitor voltage: in topologies [6,7,10] The capacitor voltage is self-balanced Fig. 1 Switched-capacitor modules that the switched-capacitor module is composed of five switches and one capacitor, in which S n1 -S n4 are switches with anti-parallel diodes and S n5 is the switch without an anti-parallel diode.When switches S n3 and S n4 are turned off but other power switches are turned on, the capacitors C n can be charged in parallel with the dc source, as shown in Fig. 1b.When the switches S n3 are turned on and other switches are turned off, the capacitors C n are discharged in series with the dc source, as shown in Fig. 1c.Similarly, the switches S n4 are turned on and other switches are turned off in Fig. 1d, and the capacitors C n are discharged by the dc source, but the polarity of the output voltage is opposite to the state of Fig. 1c.Obviously, the maximum voltage stress of switches S n3 and S n4 are kept within 2V dc , and the MVS of other switches are kept within V dc .Thus, the total standing voltage (TSV) of the presented module is expressed as: Therefore, the proposed switched-capacitor module can achieve twice the voltage gain and effectively reduce the voltage stress of switches.

Proposed topology
Figure 2 presents a generalized SCMLI.It can be seen that the topology is composed of multiple switchedcapacitor modules which can raise the output levels and obtain a higher boosting factor.To facilitate analysis, this study takes the proposed seven-level inverter as the instance in Fig. 3a, which can achieve the capacitor voltage self-balancing and obtain triple voltage gain with two capacitors.The H-bridge is eliminated due to the inherent inversion capacity.The seven working modes of the inverter are shown in Fig. 3b-h when the output levels are: ± 3V dc , ± 2V dc , ± V dc and 0.

Operating principle
The working state of the 7-level topology is presented in Table 2, wherein the bold values are the alternative operating states which can obtain the same output voltage level, "C", "D", and "-" demonstrate the charging, discharging, and idle modes of the capacitors, respectively.
The working principle of the inverter is analyzed as shown follows: (1) V out = 3V dc : When the switches S 13

Modulation strategy
Various modulation techniques have been applied to multilevel inverters, including space vector modulation, multicarrier modulation, selective harmonic elimination modulation.In this article, the phase disposition pulse width modulation (PD-PWM) is selected for the proposed topology due to the convenience and low total harmonic distortion (THD).
The modulation principle of a proposed 7-level inverter can be seen in Fig. 4.There are six triangular carriers e 1 -e 6 with equal amplitude A c and frequency f c , and a sinusoidal reference wave with the amplitude A ref and frequency 50 Hz (f o ).These triangular carriers are compared with reference waves to engender six pulse signals u 1 -u 6 .According to the working states, the logical groupings of switches are shown in Fig. 5.
In the PD-PWM strategy, the modulation index is dependent on the amplitude of triangular carriers and sinusoidal wave.Thus, the modulation index M varies between 0 and 1, which can be expressed as: In Fig. 4, the instants t i (i = 1, 2, 3, 4) are the intersection points of sinusoidal reference wave and triangular carriers, which are expressed as: where f o is the frequency of output voltage.When M is set to 0.9, the proposed inverter can obtain a seven-level voltage and achieve triple voltage gain. (3)

Analyses of capacitance
The proposed multilevel inverter has a self-voltage balancing ability without any auxiliary circuits.The capacitors C 1 and C 2 are charged to V dc in parallel with dc source in each cycle, which is can be seen in Table 2 and Fig. 3.The capacitance in the multilevel inverter is important to achieve multilevel output and voltage gain.Additionally, the voltage ripple of capacitors should be maintained within an acceptable range to enhance the quality of output voltage.The quality of output voltage is affected by capacitor voltage ripple, and the maximum continuous discharge has a bearing on the voltage ripple.Therefore, the capacitor voltage ripple is diminished efficaciously by choosing the appropriate capacitance.
Based on the operating principle and modulation strategy, it can be observed that capacitors C 1 and C 2 have the same operating states.Both capacitors can be discharged at ± 3V dc and ± 2V dc levels, and be charged at ± V dc and 0 levels.Therefore, the maximum discharging interval of capacitors C 1 and The capacitor voltage ripple is mainly affected by the maximum discharging amount.The output voltage and load current of the topology have the same phase under resistive load, the maximum value of load current is the middle of the integration period, and the discharge capacity of the capacitor is the largest.The output voltage and current have different phases under inductive load, the peak value of the load current is not the middle of the integration period, which reduces the discharge capacity of the capacitor.Therefore, the capacitance value calculated by the pure resistive load condition is applicable to inductive load.As can be seen from Fig. 4, the maximum continuous discharging amount ΔQ C of C 1 and C 2 within [t 1 -t 4 ] can be calculated as: where V o is the output voltage, R is the load resistance and f o is the frequency of output voltage.
As shown in Fig. 4 the output voltage V o is 2V dc at intervals [t 1 , t 2 ] and [t 3 , t 4 ], and the output voltage V o is 3V dc at interval [t 2 , t 3 ].Therefore, a further calculation can be given as: When k% is presumed the constant that describes the maximum acceptable voltage ripple, capacitances of C 1 and C 2 can be determined as: The size of the capacitor is usually set according to the principle that the capacitor voltage ripple is more than 10% of the rated voltage of the capacitor, then the capacitance is calculated by: where V dc is the voltage of capacitors C 1 and C 2 .

Comparison
To validate the merits of the proposed topology, this study compares and analyzes a total number of components, MVS and TSV in combination with the characteristics of the traditional multilevel inverters [5,8], the expandable SCMLIs [11,16,18] and the new switched-capacitor inverters [20,22,25].For the convenience of comparison, Table 3 gives the specific values of the number of devices in various comparison topologies, the maximum voltage stress MVS and the total standing voltage TSV of switches.
For the convenience of comparison, the output levels of all inverters are set to 2n + 1.The input voltage is uniformly V dc if only a single dc source is employed.The following is ( 8) (2n 2 + n)V dc 6nV dc 10nV dc /3 (8n − 4)V dc (n 2 + 9n)V dc /2 11nV dc /4 (6n − 4)V dc (7n − 2)V dc (7n − 3)V dc the detailed analysis of the topology in the existing literatures and the topology proposed in this study.

The total components
Figure 6 gives the comparison of the total components including switches, diodes and dc sources.for some existing inverters and the proposed inverter.It is not hard to see that the number of total components of the proposed inverter is less than the MLIs proposed in [5,25].The inverters in [8,11,20,22] utilize multiple dc sources to obtain more output levels, which leads to an increase in cost and limits the application scenarios.The topologies proposed in [16,18] employ H-bridge to alter the polarity of output voltage, while voltage stress on switches will increase with the growth of output levels.Comparing with the number of total devices of the SCMLIs, the proposed inverter only uses a dc source to achieve boosting factor of 3 and also reduces the voltage stress on switches which can be kept constant in the extended structure.

MVS
On the basis of the above study of the proposed working principle, the MVS of switches S n3 and S n4 are 2V dc , and the MVS of other switches are V dc .Figure 7 shows the comparison results of MVS values between the existing inverters and the proposed inverter.As the growth of output levels, the voltage stress on power switches is still kept within 2V dc , which is a significant advantage of the proposed switched-capacitor topology.
Although the inverters proposed in [16,18] utilize less devices, the MVS on power devices will raise with the growth of levels, which leads to the MVS of switches being the amplitude of output voltage.With the increase in output levels, the MVS in other topologies can be kept constant.For the extended topology, the topology proposed in [5] has lower values of MVS, but numerous clamping diodes are employed to achieve multilevel output, which needs a complex control strategy to achieve self-voltage balance.The MVS of the inverters proposed in [11,20] can be kept within V dc in the extended structure, but the voltage gain of the inverter proposed in [11] is 1.5, and the inverter proposed in [20] has a voltage gain of 2.
The proposed 7-level topology can obtain triple voltage gain, and the MSV of all power switches can be kept within 2V dc , which can efficaciously reduce the total standing voltage.Although MVS of the inverters proposed in [8,22] can be kept constant with the growth of voltage levels, multiple dc sources are employed to raise output levels and the MVS on switches is higher than the proposed topology.Moreover, the topology proposed in [25] uses more devices to obtain constant voltage stress.Therefore, the proposed inverter has great potential in the fields of medium and high voltage.

TSV
Figure 8 shows a comparison of the TSV values between the previous literatures and the topology proposed in this study.According to the chart, the TSV of several topologies increases with the growth of output levels.The TSV of the proposed inverter is greatly decreased in contrast to other inverters, which can effectively reduce the switching losses during the operation of the inverter and increase the service life of the power switches.
It can be seen from the above comparisons that the inverters proposed in [11,20] have lower values of TSV, which is beneficial to improve the efficiency of inverters.However, the voltage gain cannot be raised with the increase in output levels, and the application scenarios will be limited.The inverters proposed in [8,22] also have lower values of TSV, and the boosting factor can be raised in extended topology.However, multiple dc sources are utilized to raise output levels, which leads to an increase in cost and limits the application scenarios.The TSV of the inverters proposed in [16,18] is higher due to the use of an H-bridge, which results in the peak value of the output voltage on switches.And the inverter in [25] has higher TSV because more switches and capacitors are employed.
Compared with the above-mentioned inverters, the proposed topology has a higher boosting factor.Although the proposed inverter uses lots of switches, it does not involve other components.In addition, the MVS on switches of the proposed inverter is kept constant with a single dc source, since the topology is applicable to medium and high voltage systems.Therefore, although the proposed topology uses many switches, it still has advantages in improving the boosting factor and reducing the stress on switches compared to previous MLIs.

Simulation results
According to the above analysis, the feasibility of the proposed inverter has been checked with different conditions.The simulation model of the proposed topology is carried out in MATLAB/Simulink environment.Simulation components have been given in Table 4.According to Eq. (10) and simulation parameters, the capacitance value should  be greater than 1758 μF, so the capacitor is chosen to be 2200 μF to assure that capacitor voltage ripple can be within the required range.Figure 9 gives the simulation results, and the waveform diagram of output voltage and load current under pure resistive load are presented in Fig. 9a.It is not hard to see that the proposed topology can generate seven-level voltage and achieve a triple voltage gain.When the resistive-inductive load is used, Fig. 9b gives the waveform diagram of output voltage and load current.As shown in Fig. 9b, the load current is a sinusoidal wave.It is obvious that the inverter can carry both inductive and pure resistive loads.
The voltage ripple of capacitors C 1 and C 2 is given in Fig. 9c.The capacitor voltages can be self-balanced with low voltage ripple.And the fluctuation range is between 27 and 30 V, which satisfies the design requirements of the capacitor voltage ripple range.Figure 10 presents the Fast Fourier Transform of the proposed topology when the modulation index is 0.9.
The THD of the inverter is 19.86%, and 40th harmonic component is higher than the others since the carrier frequency is 2 kHz.The low THD can also simplify the design of the filter.

Experimental results
To validate the feasibleness of topology, this study evaluates the proposed inverter through a small experimental prototype.Table 5 shows the basic components required in the experiment.
The inverter is experimentally verified under different load conditions, and then the experimental results are analyzed.An experimental prototype of a 7-level inverter has been implemented to validate its effectiveness, as shown in Fig. 11a. Figure 11b presents a waveform diagram of output voltage and current.It's obvious that the topology can obtain a seven-level output waveform when a load is purely resistive, the amplitude of output voltage can reach 90 V. Load current is also a seven-level waveform and the maximum load current is about 1.8 A, which is consistent with the theory.
Figure 11c gives the output voltage and load current under resistive-inductive load.It's obvious that the inverter can output a seven-level staircase wave.The levels are ± 90 V, ± 60 V, ± 30 V and 0, respectively.The load current is a sinusoidal wave which works stably.Figure 11d shows the voltages of capacitors C 1 and C 2 , which fluctuate around 29 V.It is not hard to see that capacitor voltages can achieve self-balancing, and voltage ripple is kept within 3 V, which is in good argument to the above analysis.Figure 11e gives the currents of capacitors C 1 and C 2 , which behave similarly and change periodically.A peak current will appear when the capacitor is charged.It can be seen from Fig. 11e that currents amplitude of capacitors C 1 and C 2 are similar in magnitude, which is within 10 A. The above are graphs of the steady-state experiment.All in all, when the inverter starts to work, the output voltage and load current can be kept stable, meanwhile the steady-state performance is also very good.
Figure 11f, g present the output voltage and current under variable output frequency.For the experimental waveforms whose output frequency varies between 50 and 200 Hz, the proposed inverter responds immediately, and the waveform after the change is stable, which satisfies the normal working conditions of the inverter.
Figure 11h, i show waveform diagrams of output voltage and current with variable modulation indexes.The proposed inverter has a quick response and works normally.Therefore, the proposed inverter has a good dynamic performance.When the frequency and modulation degree of the inverter change greatly, the inverter can still respond quickly and work normally.

Conclusion
This article proposes a modular switched-capacitor inverter which employs a single dc source.The inverter can generate seven-level and obtain triple voltage gain.Moreover, the maximum voltage stress on switches can be kept within 2V dc due to the elimination of H-bridge.The capacitors can be charged to V dc in each cycle since voltage-self-balance ability is conducive to simplify the control strategy.Furthermore, the proposed inverter can be flexibly extended to achieve more levels and a higher boosting factor by adding switched-capacitor units.When the boosting factor is n, the output levels are 2n + 1 and the MVS of switches is still 2V dc .Simulations and an experimental prototype have been carried out to examine the practicability of the inverter.The results signify that the topology works well with variable situations.Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made.The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material.If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder.To view a copy of this licence, visit http:// creat iveco mmons.org/ licen ses/ by/4.0/.

Fig. 4 Fig. 5
Fig. 4 Modulation principle of the proposed inverter

Fig. 9
Fig. 9 Simulation results: a output voltage and current under pure resistive load; b output voltage and current under resistive-inductive load; c voltage of capacitors

Fig. 10
Fig. 10 THD of the output voltage

Fig. 11
Fig. 11 Experimental results: a experimental prototype; b output voltage and current under pure resistive load; c output voltage and current under resistive-inductive load; d voltage of capacitors; e cur-

Table 1
Comparison between the previous topologies and the proposed topology and S 23 are turned ON, capacitors C 1 and C 2 can be charged to V dc , as shown in Fig. 3b.Then output voltage 3V dc is synthesized by turning ON the switches S 1 and S 4 .(2) V out = 2V dc : When the switches S 11 , S 12 and S 23 are turned ON, capacitor C 1 is discharged in series with capacitor C 2 , as shown in Fig. 3c.Then output voltage 2V dc can be synthesized by turning ON the switches S 1 and S 4 .(3) V out = ± V dc : When the switches S 11 , S 12 , S 15 , S 21 , S 22 and S 25 are turned ON, capacitors C 1 and C 2 can be charged to V dc , as shown in Fig.3d, f.The output voltage V dc is synthesized by turning ON the switches S 1 and S 4 , while the negative output voltage -V dc can be obtained by turning ON switches S 2 and S 3 .(4) V out = 0: When the switches S 11 , S 12 , S 15 , S 21 , S 22 and S 25 are turned ON, capacitors C 1 and C 2 can be charged to V dc , as shown in Fig. 3e.Zero output level is synthesized by turning ON switches S 1 and S 3 .(5) V out = − 2V dc : When the switches S 14 and S 24 are turned ON, capacitor C 1 is discharged in series with capacitor C 2 , as shown in Fig. 3g.Then output voltage − 2V dc can be synthesized by turning ON the switches S 1 and S 3 .(6) V out = − 3V dc : When the switches S 14 and S 24 are turned ON, capacitors C 1 and C 2 can be discharged in series with dc source, as shown in Fig. 3h.The output voltage − 3V dc can be synthesized by turning ON the switches S 2 and S 3 .

Table 2
Operating states of the proposed topology

Table 3
Comparison of the proposed inverter and other structures (2n + 1 levels)

Table 4
Simulation components

Table 5
Experimental components Natural Science Foundation of China under Grant 51507155, in part by the Youth Key Teacher Project of Henan Universities under Grant 2019GGJS011, and in part by the Key R&D and Promotion Special Project of Henan Province under Grant 222102520001.