Design issues and performance analysis of CCM boost converters with RHP zero mitigation via inductor current sensing

The right-half plane (RHP) zero in the control to output voltage transfer function of a boost converter operating in the continuous conduction mode limits the loop bandwidth. By injecting a scaled version of the inductor current into the loop, it is possible to shift the zero from the right-half plane to the left-half plane, which leads to increased stability of the control loop. This solution generates a static voltage error at the output of the converter (tracking error), which may be unacceptable in practical applications. A few strategies to mitigate or correct this tracking error have been suggested. However, they have never been fully assessed. This paper thoroughly investigates the impact of the RHP zero mitigation technique on the dynamic performance of a boost converter, and identifies the complex trade-off between the system stability, transient response, and tracking error correction capability. Based on these findings, design guidelines are provided to help maximize system performance. A representative case study is considered to highlight the performance benefits and simulation results are presented to validate the analysis.


Introduction
Handheld devices with large LED displays require one or more high-efficiency step-up DC-DC converters occupying small footprints and being able to handle large instant line and load variations without impairing image quality.
Stepup converters working in the continuous conduction mode (CCM) suffer from the presence of a right half plane (RHP) zero, which constrains the closed-loop bandwidth of the converter, which affects the speed of the transient response. This zero, which is inherently present in the control-to-output transfer function, usually limits the maximum bandwidth to a fraction of the frequency of the RHP zero. A typical solution is to force the converter to operate in the discontinuous conduction mode (DCM). In this mode of operation, the RHP zero is shifted to a much higher frequency, which increases the phase margin for a given bandwidth [1]. Unfortunately, this advantage comes at the price of a large inductor current ripple, which results in higher device stress, lower efficiency, and potential magnetic core saturation. Numerous papers have been devoted to the RHP zero problem [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16]. In [3][4][5][6][7][8], the unwanted zero is either moved to a higher frequency or eliminated by modifying the power stage topology. These solutions, despite providing excellent dynamic behavior, require an extra power MOS switch or an extra inductance, which makes them unsuitable for integrated low-power converters where minimum circuit footprint is required. Ripple-based control, such as that proposed in [9,10], guarantees an inherently stable loop and can provide fast line and load transient responses. In [11], the duty cycle of a converter is kept fixed during a transition to compensate for the effect of the RHP zero. However, the major drawback of these techniques is that the switching frequency of the converter is not fixed. Instead, it depends on the circuit operating conditions. The authors of [12][13][14][15] introduced techniques to solve the RHP zero problem by acting on the loop compensator. However, either the area of the compensator is largely increased or the power efficiency of the converter is decreased since they require sophisticated computational algorithms or analog-to-digital converters with a high sampling rate.
Among the various methods to mitigate issues related to the RHP zero, an interesting approach has been recently presented by Paduvalli et al. [16]. The method exploits the left-hand plane (LHP) zero present in the transfer function from the control to the inductor current flowing in the highside power MOS. The authors demonstrate that by summing a voltage proportional to the scaled inductor current and the output voltage, as shown in Fig. 1, the RHP zero of the system is moved either to an infinite frequency (perfect cancellation) or to the LHP. By setting the value of the transimpedance RT applied to the inductor current, it is possible to change the frequency of the zero in the control-to-output transfer function, which leads to increased stability of the control loop. The advantage of this compensation method is that it adds little additional hardware on the power stage while requiring no modifications to the standard (voltagemode) compensation network. On the downside, the technique proposed in [16] results in a static voltage error at the output of the converter (tracking error). A few strategies have been suggested to mitigate or correct this tracking error. However, they have never been fully assessed. In this paper, the impact of the RHP zero shifting technique on the dynamic performance of a boost converter is thoroughly investigated, identifying the complex trade-off between system stability, transient response and tracking error correction capability. The aim of the paper is to provide design guidelines that help maximize system performance. In order to highlight the performance benefits, a step-up converter powering a large LED screen of a portable device has been considered as a representative case-study.
The input voltage V in of the converter from a standard Li-ion cells typically ranges from 2 to 4.5 V. The output voltage V out is 5 V, and the load current I load ranges from 0 to I load,max = 800 mA . In such applications, where the footprint is one of the main constraints, the converter is usually fully integrated except for the second-order LC filter. To minimize the footprints of the external inductor and capacitor, a relatively large switching frequency is typically chosen. In this study, a switching frequency f sw of 1.5 MHz, an inductance L of 2.2 mH, and a capacitance C of 44 µF are assumed. This paper is organized as follows. Section 2 is devoted to an explanation of the RHP zero mitigation technique. In Sect. 3, the bandwidth and phase margin variations across the input voltage and the load current ranges of a practical case study are analyzed. In addition, a comparison is made of three different design criteria. Section 4 discusses the tracking error and provides guidelines for designing a simple tracking error correction network. Section 5 analyses the impact of RHP zero mitigation and tracking error correction techniques on the transient performance of a converter. Section 6 presents simulation results that validate the presented analysis. Finally, conclusions are drawn in Sect. 7.

RHP zero mitigation
To obtain a stable boost converter, a proportional-integralderivative (PID) compensator is typically implemented. It provides a DC pole, two zeroes, and two high-frequency poles. The zeros are used to compensate for the poles of the output filter. Meanwhile, the two high-frequency poles are used to cancel the zero introduced by the capacitance ESR and to reduce the ripple at the switching frequency. These poles are not accounted for in the following analysis since their impact on stability and transient response is negligible. Under this assumption, the loop gain transfer function of the boost converter with a type-III compensator is written as follows: where: zl and zh are the time constants of the low-frequency and high-frequency zero of the compensation network. z,rhp is the time constant of the RHP zero. The term s s 2 + s + 1 accounts for the poles of the LC filter.
Neglecting the capacitance ESR, the RHP frequency becomes: where R load = V out ∕I load is the load impedance, and D � = 1 − D = V in ∕V out . In battery-powered applications, the input voltage V in , as well as the load current I load , vary across a relatively wide range. As a result, the RHP zero frequency, which is a function of those two parameters, Fig. 1 Simplified schematic block of a boost converter with inductorinformation-based RHP elimination is variable along with the ranges of V in and I load . The loop stability has to be guaranteed under the limiting condition when the RHP zero is at its minimum frequency. This occurs for the minimum values of R load and D ′ , or, in other terms, for the minimum V in and the maximum I load . Employing the RHP zero mitigation technique proposed in [16], whose diagram is schematically represented in Fig. 1, the expression of the zero frequency in (2) becomes: where n is the attenuation factor with which the boost output voltage is applied to the compensator input. The negative term at the denominator of (3) is directly proportional to the transimpedance R T , and is responsible for the shifting of the RHP zero. This shift is exploited to widen the loop bandwidth with respect to the previous case. In particular, when the condition R T > L nCR load D ′ is met, z,rhp becomes negative, which means the zero is brought to the LHP. However, in practice, stability has to be assured over all the possible working conditions. Since nR T C is fixed, while L R load D ′ depends on the input to output voltage ratio and the load current, R T should be chosen large enough to move the zero to the LHP even in the worst possible case. As a result, the frequency of the resulting LHP zero is dependent on D ′ . The natural frequency of the complex poles 0 = D � √ LC is also proportional to D ′ . Thus, it can be concluded that, following this approach, the LHP zero tracks the complex pole pair at least to the first order, and the control system can be reduced from a type-III PID to a simple type-II proportional-integral (PI) controller.

Stability analysis
In this section, the performance of the RHP zero-mitigation technique is assessed in a practical case, where stability has to be guaranteed across the entire range of input voltages and load currents. Considering this specific case study, the minimum frequency of the RHP zero from (2) is at f z,rhp = z,rhp ∕(2 ) = 72.3 kHz . To guarantee a sufficient loop phase margin with a type-III compensator, the bandwidth is limited to about f z,rhp ∕5 , i.e. 14 kHz, which is significantly lower than the switching frequency. Using the RHP mitigation technique in [16], some degrees of freedom exist in the positioning of the singularities. Thus, three different strategies are studied and their performances are compared.
A. R T is chosen to cancel the RHP zero, i.e. to shift it to an infinite frequency.
. R T is chosen to move the RHP zero to the LHP at an angular frequency equal to 1∕ zh , and the controller is reduced to a type-II PI. C. R T is chosen to move the RHP zero to the LHP at an angular frequency equal to 1∕ zl , and the controller is reduced to a type-II PI.
For a fair comparison, the zeroes are placed at the same frequencies, f zl = 5 kHz and f zh = 25 kHz , in the three cases, (A), (B) and (C). By eliminating the RHP zero, the loop bandwidth is no longer restrained. However, it cannot exceed about one tenth of the switching frequency f sw to ensure the validity of the linear continuous-time model. Thus, in the three cases, the bandwidth is kept below about 150 kHz, under all working conditions.

Stability in case (A)
To remove the RHP zero or in other words to move it to infinity, it is imposed that the denominator in (3) is null. Assuming a voltage attenuation factor of n = 5, the required transimpedance value is R T = 4 mΩ . In this case, the loop gain can be re-written as: is the filter quality factor, and the gain nD � is given by the product of the gain of the control-to-output transfer function and the compensator gain G C0 . The widest loop bandwidth is achieved when the complex poles in (4) are at their maximum frequencies, i.e. when V in is at its maximum and the load current is zero. To have a maximum bandwidth of 150 kHz under this condition, the required compensator gain of G C0 = 111 dB is obtained from (4). Figure 2 shows the variation of the loop-gain magnitude and the phase margin for three different input voltages V in and a fixed load current of I load = 0.8 A . To better verify the data, each of the diagrams is computed using both a MAT-LAB continuous-time model (continuous line) and a AC periodic simulation in SIMPLIS (dotted line). The large bandwidth variation is mainly given by a shift of the complex pole pair frequency 0 . However, the inaccurate cancellation of the RHP zero is responsible for the larger phase margin. At low load currents, when the term L negligible with respect to nR T C , the minimum LHP zero frequency is achieved, whose expression is: Using the parameters in this case study, the minimum LHP zero frequency from (5) is 163 kHz, which is very close to the maximum crossover frequency of 150 kHz. As a result, the slope of the loop gain magnitude near the crossover goes above − 20 dB/dec. This effect increases the sensitivity of the loop gain crossover frequency with respect to the process, voltage and temperature (PVT) variations.

Stability in case (B)
The second design approach is to select R T so that the RHP zero is shifted to the LHP and used in place of the high frequency zero zh of the compensator. Applying this condition to the worst case of the minimum V in and the maximum I load , the required transimpedance is given by: Taking into account the parameters of this case study, the required transimpedance from (6) is R T = 15 mΩ . The overall loop gain can be written as: In the previous case, the largest loop bandwidth should not exceed 150 kHz. Thus, a compensator gain G C0 of 118 dB is needed in this case. Figure 3 shows the loop gain , magnitude and phase margin at different Vin values. In the previous case, the data are obtained using both a continuoustime model (continuous line) and a periodic small-signal model (dotted line). The magnitude plot shows the expected shift of the complex pole pair with the input to output ratio. Unlike the previous case, this effect does not seem to significantly influence the crossover frequency and the phase margin. This behavior can be explained by recalling that the LHP zero and the complex poles have the same dependency on D ′ to the first order. Due to this singularity tracking, the converter bandwidth and phase margin remain relatively stable over the entire working range.

Stability in case (C)
In this case, the RHP zero is moved to the LHP and used in place of the low frequency zero zl of the compensation network. In the worst-case condition of the minimum V in and the maximum I load , the required transimpedance has the same expression in (6) but with zl instead of zh . Solving the equation a value of R T = 60mΩ is obtained for the case study. The loop gain is: Thus, the value of the compensator gain G C0 to obtain the maximum bandwidth turns out to be G C0 = 120 dB. Figure 4 shows the loop gain magnitude and phase margin for the three values of V in . The diagrams are computed with the same technique as the previous two cases. The lower sensitivity to V in with respect to case (B) follows from the larger value of nR T C which makes it dominant in the denominator in (3). This allows for a better frequency tracking of the zero and the complex poles. Comparing the three design cases, it can be concluded that by increasing the R T value, the loop gain crossover frequency, and the phase margin become less dependent on the operating conditions (input voltage and load current). In particular, choosing a value of R T as in case (A) or lower is not recommended since this leads to a large variation in terms of the bandwidth and phase margin at different operating conditions, which impairs the robustness of the converter. Case (B) and case (C) are better choices since they have been proven to be less susceptible to RHP variation.

Tracking error correction
Adopting the above-discussed RHP zero mitigation technique, the reference voltage of the compensator is not directly compared with the voltage of the filter capacitor. Instead, it is compared with the sum of the output voltage and the scaled inductor current. Thus, at the steady-state, the following equation holds: where I ind is the average inductor current. This means that the output voltage is affected by the static error V tr = nR T I ind .
The first parameter affecting V tr is the average inductor current, which depends on the output load current I ind = I load D � , where is the transfer efficiency. The maximum error is obtained at the maximum load current and the minimum input voltage. Considering a transfer efficiency of 100%, the maximum average inductor current I ind in this case, the study is equal to 2 A. The second parameter influencing the tracking error is the transimpedance R T , whose value depends on the chosen design strategy. Case (A) entails the lowest R T , which leads to minimum error. On the other hand, case (C) results in the largest offset. The maximum tracking error calculated for the three design strategies (A), (B), and (C) are 40 mV (0.8% of V out ), 150 mV (3%), 600 mV (12%), respectively. In applications where the static error is unacceptable, an error correction strategy must be employed. To understand whether the tracking error can be eliminated without impairing the RHP zero mitigation technique, we can analyze the transfer function from the duty-cycle to the compensator input T dc (s) of the system in Fig. 1: where the first term of the sum is the control to the output transfer function, T do (s) , divided by n. Meanwhile, the second one is the control to inductance current transfer function, T di (s) , multiplied by R T . After manipulating (10), T dc can be written as: As long as the term (11) is ≪ 1, it can be concluded that only the AC value of the T di (s) transfer function affects the RHP zero mitigation. Thus, the tracking error can be removed in principle by eliminating the DC value of the scaled inductor current before injecting it into the output node. As suggested in [16], this task can be accomplished by applying a high-pass filter to the scaled inductor current (see Fig. 5). The pole of the high-pass filter at an angular frequency of lp has to be low enough to preserve the AC content of the control to the inductance transfer function. Starting from (11), neglecting the term , in (11) the following is obtained: Eq. (12) can be approximated with (11). This means that the (10)

Load transient response
The load transient response is determined by the closedloop output impedance, Z out (s) . This can be computed from the flowgraph of the circuit shown in Fig. 5. The flowgraph is shown in Fig. 6, where ṽ g represent a variation of the input voltage, Ĩ load represent a variation of the load current, G C (s) is the compensator transfer function, and R T (s) = is the high-pass filtered transimpedance R T . Solving the flowgraph under the hypothesis of ṽ g = 0 yields: where the loop gain G L (s) must be replaced with the loop gain from (4) or (7) depending on the type of design adopted. For comparison, the output impedance of a boost converter with no RHP zero mitigation can be calculated as: Notice that the expression of Z out no−mit is similar to that of the first term of Z out , with the loop gain G L (s) being the only difference. To assess the impact of the RHP zero mitigation on the load transient response, the transient response obtained from (13) is compared with that obtained from (14). For the sake of simplicity, the peak output voltage variation ΔV out caused by a step current variation ΔI load is considered. Under simplifying assumptions, the peak output voltage variation is: The magnitude of the compensator gain depends on the target zero dB crossing of the loop gain, which in turn depends on the minimum frequency of the RHP zero. Since the two zeroes of the compensation network are placed to eliminate the complex pole pair, the zero dB crossing frequency can be approximated as that of an integrator V out G C0 no−mit snD � . Considering the maximum bandwidth to be a fraction of the RHP zero frequency c = z,rhp , the voltage variation in (15) can be rewritten as: The voltage variation in (16) must be compared with the corresponding term generated by (13). The output impedance in (13) includes two terms, the first is similar to the closed-loop impedance of a standard boost converter, and the second is generated by the RHP zero mitigation technique. The first term leads to ΔV out1 which has the same expression reported in (15). The only difference is the DC value of the compensator gain ( G C0 instead of G C0 no−mit ). Considering a large loop gain, the second term This contribution depends on the input to output ratio, has a magnitude proportional to the transimpedance value R T and does not depend on the system bandwidth. Combining (15), (16), and (17) yields: When the ratio expressed in (18) is less than 1, the load transient performance of a boost converter with RHP zero mitigation is better than that of a standard boost converter limited by a RHP zero. For this to occur, the transimpedance R T must fulfill the following inequality: Notice that the compensator gain is proportional to the system bandwidth. Thus, the following inequality holds true G C0 ≫ G C0 no−mit since the RHP zero mitigation provides an increase in the bandwidth. Accordingly, the term inside the parenthesis is ≃ 1. Combining (19) with the equation describing the RHP zero in (2) yields: Solving this inequality under the worst case, i.e. with V in = V in,max and = 5, yields R T < 30 mΩ . In contrast to the conclusions drawn in Sect. (3), the load transient performance improves when R T decreases. In particular, case (A) provides a significant improvement in the load transient performance. Meanwhile, case (C) has a load transient behavior far worse than that of a boost converter limited by RHP zero.

Line transient response
The line transfer function is obtained starting with the flowgraph in Fig. 6 considering no-load current variation, i.e. ĩ = 0.
(17) ΔV out 2 = − ΔI load nR T D � . (18) where the loop gain is the one computed in the previous section. In the load transient case, (21) includes two contributions. The first contribution is the standard line transfer function of a boost converter, and the second contribution is generated by the RHP zero mitigation technique. For comparison, the line transfer function of a standard boost converter is: The load transient case (22) is similar to T line 1 (s) except for the loop gain. To assess the line transient performance, the peak output voltage variation obtained from (21) is compared with the one given by (22). The peak variation of the output voltage for a step variation of the input voltage ΔV in in the case of a standard boost converter without zero mitigation is: where Δ = zh − zl . The value of the compensator gain is related to the zero dB crossing of the loop gain which is related to the frequency of the RHP zero. By estimating the compensator gain G C0 no−mit as that of an integrator G C0 no−mit V out snD � and assuming the crossover frequency to be c = rhp , (23) can be rewritten as: This result should be compared with the peak voltage value derived from (21). As can be seen in Sect. 5.1, the first term in (21) leads to the contribution of ΔV out 1 , which has the same expression as that reported in (23) but for the DC value of the compensator gain ( G C0 ≫ G C0 no−mit ). Considering a large loop gain, the second term of (21) T line 2 (s) can be approximated as T line 2 (s) = − . This leads to a peak output voltage variation, considering a step input voltage ΔV in , and is equal to: This contribution is proportional to the steady-state load current I load , and it does not depend on system bandwidth. Combining (23), (24), and (25) yields: (23) When the ratio in (26) is less than 1, the boost converter with RHP zero mitigation provides some advantage over the standard boost in terms of line transient response. For this to happen R T must fulfill the following inequality: As concluded in Sect. 5.1, the term in the first parenthesis is ≃ 1. Combining (27) with (2) in the worst-case scenario of V in,min and I load,max the inequality (27) becomes: In agreement with the conclusions drawn in Sect. 5.1, the smaller the value of R T the better the performance of a boost converter with RHP zero mitigation in terms of line transient response. Solving (27) with = 5, a transimpedance value R T < 115 mΩ is obtained. This value is larger than the transimpedance values calculated for all three of the case studies, which means that the RHP zero mitigation technique always improves the line transient performances when compared with a standard boost.

Simulation results
To validate the analysis, the dynamic performance of a boost converter with RHP zero mitigation has been simulated for the three design cases, (A), (B), and (C), using Cadence-Virtuoso. The validation includes two steps. First, the line and the load transient responses for the boost converter in Fig. 5 with different design strategies are compared and commented upon. Then the line and load transient responses of a boost with design (B), which is the one with a better trade-off between dynamic performance and stability, are compared with those of a standard boost converter without RHP zero mitigation. All of the results shown in this section refer to a frequency of the compensation pole lp that is equal to 1∕4 of the zero in (3). This choice does not significantly affect the stability of the system, which remains close to the system estimated in Sect. 3. The main parameters used for the simulation of each case study are summarized in Table 1. The line transient response is simulated considering a fixed load current of 0.8 A and an input voltage variation of V in = 2 V → 2.5 V for the three case   Figure 7 shows a comparison of the transient response obtained from Cadence-Virtuoso and the linear step response given by (21). The comparison shows that design case (C) has a larger transient response with respect to that of the case (A) and case (B) designs, due to the higher R T value. From Fig. 7, it is possible to see that the peak voltage variation for case (C) is about 120 mV, which is in close agreement with the value obtained from the first-order estimation in (25)  The load transient response has been simulated considering a load current step variation of ΔI load = 0.1A → 0.8A with a fixed input voltage of V in = 2V . Figure 8 shows a comparison between the transient response obtained from Cadence-Virtuoso and the linear step response given by (13). Similar to the line transient case, the peak voltage obtained in the case (C) design is dominated by the contribution of Z out 2 (s) in (13), and its magnitude is much higher than the other design cases due to the large R T value. The peak voltage variation from Fig. 8 is about 400 mV which is slightly lower than the estimation in (17) 525 mV due to the effect of the high-frequency poles neglected in the analysis. The peak voltage in (B) 120 mV is still dominated by the second contribution in (13), and its amplitude is well predicted by (17): 131 mV. Finally, case (A) (90 mV) presents a load transient response where the two contributions in (13) have similar impacts on the output voltage variation.
For this reason, a fair estimation of the peak voltage variation can be achieved by summing the values provided by (17) and (15), which yields 89 mV. Concerning the transient recovery time, case (C) and case (B) are mainly determined by the time constant 1∕ lp , which is the load transient response in (13) dominated by the second term. Note that the value of the time constants 1∕ lp in case (C) and case (B) are different, and are proportional to R T . Finally, the recovery transient in case (A) is dependent on both 1∕ zh and 1∕ lp , since the two contributions in (13) are similar in magnitude.
To complete the validation, the load and line transient responses of the case (B) are compared with those of a boost converter where the crossover frequency of the control loop c is limited to a fraction zrhp ∕4 of its RHP zero. However, this design leads to an unstable converter since c < zh . To reach a phase margin of about 40°, the frequency of the zeroes and the loop gain have been changed to: zh = 2 10 kHz , zl = 2 3 kHz , and G C0 = 87 dB . The transient responses of the two systems for a line voltage  . 9 Line transient comparison of a system with zero mitigation with respect to a system without it. The load current is 0.8A and the input voltage variation is ΔV in = 2V → 2.5V variation of ΔV in = 2V → 2.5V and a fixed load current of I load = 0.8A are shown in Fig. 9. As expected from the analysis in Sect. (5), the RHP zero mitigation provides an improvement in the line transient response of the system provided that the maximum the achievable crossover frequency of the boost converter is limited by the presence of an RHP zero. Finally, a comparison of the load transient responses of the two systems is shown in Fig. 10. The simulation has been carried out with a fixed input voltage of 2 V and a load current variation of ΔI load = 0.1A → 0.8A . The difference between the two transient responses is very small even if the loop crossover frequency of the boost with RHP zero mitigation is about a factor of 8 higher than that of the boost with no RHP zero mitigation. This result is in an agreement with the analysis in Sect. (5), which demonstrates that the advantages of the RHP zero mitigation technique in terms of load transient performance are limited.

Conclusion
This paper fully addresses the impact of the RHP zero mitigation technique on the dynamic performance of a boost converter. A first trade-off is identified between system stability and transient response, where the transimpedance R T is applied to the inductor current to move the zero from the RHP to the LHP is the main trade-off parameter. The role of the tracking error correction network is analyzed as well. The analysis shows a second trade-off between the static precision and the transient response of the output voltage. Based on these findings, design guidelines are provided to help maximize system performance. Different design strategies have been applied to a realistic case-study and compared with the same boost converter without zero mitigation, which demonstrates that that an optimal choice of R T can greatly improve both the stability and the line transient response. On the other hand, the improvement in terms of load transient response is only marginal, even if the optimal design criteria are met. Circuit simulations performed with Cadence-Virtuoso are presented to validate the analysis. Work is ongoing on the identification of alternate trackingerror correction networks capable of breaking the trade-off between the static precision and transient response of the output voltage.
Funding Open access funding provided by Politecnico di Milano within the CRUI-CARE Agreement.
Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creat iveco mmons .org/licen ses/by/4.0/. Fig. 10 Load transient comparison of a system with zero mitigation with respect to a system without it. The input voltage is 2 V and the load current variation is ΔI load = 0.1A → 0.8A