AC/DC Side Split Capacitor Power Decoupling Circuit

Single-phase inverters have a wide range of applications in many fields, but there are inherent double frequency problems, and double frequency fluctuations can easily cause system instability. This paper proposes a mid-point common-mode injection power decoupling circuit. The advantage of this topology is that there are no additional switching devices and only the original DC side support capacitors and filter capacitors of the H-bridge inverter can be used to buffer the double frequency power. The half-bridge structure of this topology enables the AC side capacitors to operate positively and negatively, which can reduce the selection of the withstand voltage of the decoupling capacitor. Simulation and experimental results prove that the method can effectively suppress the secondary ripple on the DC side. The final data shows that the topology can effectively improve the system efficiency after decoupling.


Introduction
Single-phase inverters play a very important role in various applications, However, the double frequency power on the AC side causes a secondary ripple on the DC side, which affects the performance of the entire system [1]. The commonly used method in engineering applications is to connect large electrolytic capacitors in parallel on the DC side, but electrolytic capacitors have disadvantages such as large volume, short life, and low reliability [2]. Therefore, many active decoupling methods have been proposed. Active decoupling is mainly composed of control algorithms and decoupling topologies. Generally, the decoupling topology includes two parts: the decoupling unit and the original converter. According to whether the decoupling unit and the original converter switch are multiplexed or not, the active decoupling topology can be divided into dependent decoupling and independent decoupling. The independent decoupling circuit usually keeps working independently with the original converter [3][4][5][6][7][8][9][10][11][12]. However, independent decoupling usually requires more switching control capacitors or inductance compensation systems for double frequency power. In the recent literature, an additional H-bridge control capacitor voltage is connected in parallel on the DC side [3]. There is also an option to compensate for the double frequency in the form of a series H bridge in the system [4], 5. Literature [1][2][3][4][5][6][7][8][9][10] adopts the method of using a buck circuit as an independent decoupling unit on the DC side. In addition to using the basic circuit as an independent decoupling unit, literature [11], 12 adds a bridge arm on the DC side to control a group of split capacitor voltages to achieve the purpose of compensation. Independent decoupling methods generally require more switches, and the overall system cost is relatively high. Therefore, many scholars study dependent decoupling methods.
The dependent decoupling mainly forms a power decoupling unit by multiplexing the switch with the original converter. therefore, some dependent decoupling methods can reduce the number of switches and reduce costs compared to independent decoupling. Literature [13] adds a switch based on the original H bridge, plus a diode and an energy storage inductor to form a new power decoupling loop. In addition, 1 3 there is a method to control the capacitance and inductance by adding an additional bridge arm and the original bridge arm of the H bridge [14],15. However, this kind of dependent decoupling still does not have a high utilization rate of the original switch and requires additional bridge arms, which increases the cost and loss of the entire system. To reduce the cost of the system and effectively suppress the secondary ripple, a differential inverter based on the series boost type is proposed [16],17, This topology has no additional switching devices, and the capacitor voltage stress is higher than the input voltage. Similarly, a differential buck inverter without additional switching devices is proposed [18], 19, which has the problem of low utilization of decoupling capacitors, and there will still be low-frequency ripples on the DC side after decoupling. Regarding the power decoupling control mechanism of the differential inverter, the method of compensating for the double frequency through the combination of the double frequency voltage and the DC bias voltage is proposed in [16], 19. After compensating for the double frequency power of the system, quadruple frequency ripple pulsation will be introduced, which cannot achieve precise decoupling. The use of fundamental frequency voltage injection decoupling capacitors is proposed in [20], which avoids the extra low frequency derivation, but adds extra bridge arms. This paper starts with the shortcomings of the existing active decoupling methods, which are mainly due to excessive switching devices, low utilization of decoupling capacitors, and low decoupling accuracy. A mid-point commonmode injection differential buck inverter is proposed, which uses only the original support capacitors and filter capacitors on the DC and AC sides of the H-bridge inverter to connect two sets of symmetric capacitor split points to provide a loop for the double frequency power. And through the fundamental frequency common mode voltage injection, so that the system does not introduce quadruple frequency ripple. Compared with the traditional differential buck inverter, it is proved that this topology can effectively improve the utilization rate of the capacitor. The capacitor voltage stress is correspondingly reduced, and a smaller-volume film capacitor can be used. Finally, the actual verification data shows that the efficiency of the topology is improved after decoupling. Figure 1 shows the midpoint common mode injection differential topology. The main circuit is a traditional H-bridge. The original support capacitors and filter capacitors on the DC side and AC side are split, and the midpoints of the two sets of symmetrical capacitors are connected to supply circuit for double frequency Power. This topology can be decomposed into two buck circuits, in which inductor L 1 , capacitor C 1 , switching G 1 and G 2 constitute the left half of the buck converter, and inductor L 2 , capacitor C 2 , switching G 3 and G 4 constitute the right half of the buck converter. The two half-bridge structure forms make the AC side decoupling capacitor have no DC offset and improve the utilization rate of the decoupling capacitor.

Without Decoupling Analysis
Without decoupling, the AC side outputs a sinusoidal voltage, and the voltages of the left and right bridge arm decoupling capacitors C 1 and C 2 are In formula (1) is the output voltage frequency, V g is the output voltage amplitude, the relationship between the output voltage and the voltage of the two capacitors is as follows According to formula (1), the current of the two capacitors can be obtained as The common-mode neutral current is In the case of a resistive load, the output current is where I g is the output current amplitude, according to Eq. (1)-(5), the instantaneous power on the AC side can be expressed as follows: If only the DC side capacitor is used to absorb the secondary ripple, a larger capacitance electrolytic capacitor is required. To use film capacitors to replace large electrolytic capacitors, a common mode voltage can be injected into the AC side to achieve the purpose of electrolytic capacitor removal by controlling the common mode component.

With Decoupling Analysis
To compensate for the double frequency power generated on the AC side, complete decoupling can be achieved by injecting the fundamental frequency voltage into the decoupling capacitor. To maintain a constant sinusoidal output, the injected common mode voltage is the same frequency and the same amplitude, the decoupling capacitor C 1 and C 2 voltage is B is the amplitude of the injected common mode voltage. According to (1)- (7), the capacitive current can be obtained as After injecting the fundamental frequency common mode voltage, the common mode current flowing through the common mode neutral line is The symmetrical flow of the same common mode current through the split capacitor C 3 and C 4 on the DC side is The sum of the power of the two capacitors on the DC side P c3 and P c4 and the power of the two capacitors on the AC side P c1 and P c2 is exactly complementary to the double frequency power on the output side.

Analysis of Current Stress and Capacitor
Voltage Stress

Analysis of Switch Current Stress
After the common mode voltage is injected, the decoupling inductor current is mainly composed of output current, common mode current, and differential mode current.
Because the switch current and the inductor current have a duty ratio D i proportional coefficient relationship To observe the influence of the capacitance on the current stress of the switch, suppose the output voltage amplitude is 164 V and the output current amplitude is 0.82A. The current form is as follows In formula (14) Figure 2 is a curve diagram of the relationship between the capacitance value of the capacitor and the current of the switch. The curve shows a slight increase in current with decoupling compared to without decoupling, and as the capacitance changes, the current difference does not change significantly. Therefore, the injection of common-mode voltage will not excessively increase the current stress of the switch bridge arm.

Capacitor Voltage Stress and Suitable Capacitor Value Selection
According to the above analysis, after the common mode voltage is injected, the double frequency power of the system can be compensated, but the common mode voltage will increase the current stress of the switch and the (12) Fig. 2 Switch stress change curve 1 3 voltage stress of the capacitor. The capacitance value has an impact on the injected common mode component as well as the switch's current stress. The following will specifically discuss the impact of the capacitance value on the capacitor voltage stress with decoupling and without decoupling, so that the suitable capacitance value range can be determined. According to formulas (7), the maximum capacitor voltage with decoupling is Common-mode voltage injection will increase the capacitor voltage stress. To avoid over-modulation problems and ensure sufficient output voltage, a suitable range of common-mode voltage must be selected. The red dotted line in Fig. 3 shows the DC side voltage. The maximum voltage on the capacitor should not exceed this range. In the variable range of the capacitor value, the capacitor voltage with decoupling is less than the DC input voltage. Figure 3 shows that the common mode voltage is relatively greatly affected by the capacitance value of 10μF-50μF, and there is a negative correlation in this interval. In the interval greater than 50μF, the capacitor voltage tends to be stable with the change of the capacitance value, as shown by the dotted circle in Fig. 3 According to Fig. 2, it can be observed that a larger capacitance value will increase the stress of the switch, and the change of the current stress of the switch will increase, and the capacitance should not be large. It is possible to choose a 60μF trade-off.

Inductor Design
In the SPWM inverter, the output LC filter of the inverter is mainly used to filter out the harmonics of the switching frequency and its adjacent frequency bands, so the cutoff frequency f n of the output LC filter of the SPWM inverter needs to be much lower than the switching frequency f s , generally take the cut-off frequency of the LC filter as 1/10 of the switching frequency.
After calculation, L ≥ 0.422mH, in order to obtain better filtering effect, 1mH is selected comprehensively.

Comparison of this Topology
with Differential Buck Inverter Figure 4 shows the topology of the differential buck inverter. The number of switches in the topology proposed in this paper is consistent with the literature [18]. The AC side capacitor split point of the new topology is connected to the DC side supporting capacitor split point to form a halfbridge structure. The proposed topology is compared with the traditional buck inverter, the utilization rate of the AC side capacitance of the two is different, and the number of capacitors is different. There are also differences in decoupling control methods due to different capacitance distribution structures and split-point connection methods. It is necessary to conduct a detailed comparative analysis of the two circuits.

Capacitance Functional Difference
Both topologies have differential mode and common mode output under decoupling conditions. In the case of differential mode output, the DC side capacitors of the two topologies are used as support capacitors, and the AC side output capacitors are both used as differential mode output. When used as a common-mode output, the DC-side capacitor of the topology in this paper can be used as a supporting capacitor and can also be reused as a decoupling capacitor. The Assuming the capacitance value C 1 = C 2 = C 3 = C 4 , we can get Considering the capacitive reactance of the system's common-mode loop, the topology of Fig. 1 is about half of that of Fig. 4.

Capacitor Voltage Utilization
Considering the voltage of the decoupling capacitor, the traditional differential buck circuit always has a DC offset during the decoupling process, resulting in low utilization of the decoupling capacitor. Figures 5 and 6 are the two topological decoupling capacitor voltage comparisons under the same power and output voltage. From Fig. 6, There is about 225 V DC offset. Figure 6 decoupling capacitor voltage peak is higher than Fig. 5.
According to Figs. 5 and 6, the energy efficiency of the proposed topology decoupling capacitor is significantly higher than that of the traditional Buck differential decoupling capacitor. From the formula (22) the capacitor energy storage formula, the utilization rate of the capacitor energy can be quantified. The expression of capacitor energy utilization is as follows: In formula (22), C is the capacitance value, V min is the voltage Minimum value, V max is the voltage amplitude. The capacitor voltage in Fig. 6 only exists on the positive half axis. According to formula (22), the energy utilization rate of the capacitor is about 79.75%, The two capacitors on the output side of the topology proposed in this paper operate positively and negatively, and the energy utilization rate can reach 100%.

Analysis of Control Mode and Derivative Ripple
A decoupling circuit that uses capacitors to buffer the secondary ripple power. The decoupling capacitor voltage is in the form In [16]- [19], the secondary ripple injection is selected, and the double frequency power is generated through the combination of secondary ripple voltage and the DC component v d , but this method is easy to derive additional harmonics, as shown in Table 1, in this case, a 1 = 1, a 2 = 2, the quadruple frequency ripple will be derived after the secondary ripple is eliminated in the system.
In this paper, a half-bridge structure is adopted, the decoupling capacitor voltage has no DC offset, and the injected common mode voltage is the fundamental frequency component. As shown in Table 2, a 1 = a 2 = 1, there is only double frequency power in the system, and the quadruple frequency harmonic power shown in Table 1 will not be derived.

Further Remarks
Because the AC side capacitor can operate both positively and negatively, there is no DC offset, thereby the capacitor can choose a lower withstand voltage. This paper chooses  Figure 7 shows the control loop of the power decoupling circuit. The loop includes the feedback process of sampling voltage and sampling current. According to Eqs. (12), the common mode current component i Lcon can be obtained by adding the sampled inductor current, and the differential mode current component i Ldiff can be obtained by subtracting the sampled inductor current. Similarly, according to Eqs. (7), differential mode voltage v diff can be obtained by subtracting the two types, and the common mode voltage v con can be obtained by adding the two types. Therefore, the common mode and differential mode can be independently controlled for the proposed circuit.

Power Decoupling Control
The classic voltage-current double-loop control used in Fig. 7, the simplified form of the transfer function is K p is the proportional coefficient, K i is the integral coefficient. The PI parameters of the voltage controller in the common mode loop are set to k p = 0.0005, k i = 0.01, and the PI parameters of the current controller in the common mode loop are set to k p = 20, k i = 0.001. The PI parameters of the voltage controller in the differential mode loop are set to k p = 0.1, k i = 0.01, and the current controller parameters in the differential mode loop are set to k p = 30, k i = 0.1.

Simulation Results
The simulation parameters are shown in Table 3. Figure 8 shows the DC side current waveforms before and after decoupling, the waveforms of capacitors C 1 and C 2 without decoupling and with decoupling, and the waveforms of capacitors C 3 and C 4 with decoupling. Figure 8a shows the current waveform of the DC side before decoupling. Since there is double frequency power on the output side, there is an obvious double frequency fluctuation on the DC side before decoupling. The frequency is 100 Hz, which is consistent with the theory. The maximum value of the pulsating current is 0.45A, the minimum value is -0.1A, the DC side current after decoupling is shown in Fig. 8b, the simulation achieves complete decoupling, and there is only a DC bias of 0.18A. Figure 8c and d show the voltages of capacitors C 1 and C 2 before and after decoupling, as well as the output voltage waveforms. When not decoupling, the phase difference between the two capacitor voltages is 180°, and the decoupling capacitor voltage amplitude is 82 V, the output voltage amplitude is about 164 V. When the common mode voltage is injected, the output voltage amplitude remains unchanged at 164 V, the voltage amplitude of the decoupling capacitor C 1 is about 113 V, and the voltage amplitude of the capacitor C 2 is  Amplitude Fig. 7 The proposed topology control system about 90 V. The voltage stress of capacitor C 1 is higher than that of C 2 . Figure 8e shows the voltage waveforms of capacitors C 3 and C 4 after decoupling. The maximum decoupling voltage is 287 V, the minimum value is 163 V, the DC offset is 225 V, the ripple component is 50 Hz, and only the injected common mode voltage is included.

Experimental Result
To better prove the above theory, a prototype model is built as shown in Fig. 9. The experimental parameters are shown in Table 4. Figure 10a shows the waveforms of capacitor voltage, output voltage, and DC side current without decoupling. The voltage phase difference between capacitor C 1 and C 2 is 180°, the voltage amplitude of the capacitor is 82 V, which is a positive and negative symmetrical AC component, without DC bias, the output voltage amplitude is about 164 V. Before decoupling, the DC side current has obvious double frequency fluctuations. Figure 10b shows the waveform with decoupling, the output voltage remains unchanged, the voltage of the decoupling capacitor is asymmetrical, and the amplitude of the capacitor voltage C 1 is slightly larger than the voltage of the capacitor C 2 , and the maximum voltage of the capacitor C 1 is about 113 V, the maximum voltage of capacitor C 2 is about 90 V. After decoupling, the DC side current has no double frequency pulsation. Figure 11 shows the two sets of different capacitor voltage waveforms and output voltage waveforms with decoupling. Capacitor C 1 has no DC bias, and the capacitance utilization rate is high. Capacitor C 3 is a DC side capacitor with 225 V DC bias. The maximum voltage of capacitor C 3 is about 287 V, and the minimum is about 163 V. The DC side of Fig. 8 Simulation waveform of the proposed circuit. a DC side current without decoupling, b DC side current with decoupling,c Output voltage, capacitor C 1 and C 2 voltage waveform without decoupling, d Output voltage, capacitor C 1 and C 2 voltage waveform with decoupling, e Voltage waveforms of capacitors C 3 and C 4 with decoupling Fig. 9 Experimental prototype of the proposed differential inverter Switching frequency 10 kHz --capacitor C 1 does not contain differential mode components. Therefore, the AC components in the voltages of capacitors C 3 and C 4 are lower than those of C 1 and C 2. Figure 12 shows the FFT analysis without decoupling and with decoupling of the current on the DC side. Before decoupling, the 100 Hz component on the DC side is larger, and the 100 Hz component after decoupling is lower. Figure 13 shows the decoupling transient capacitors C 1 and C 2 voltage, output voltage, and DC side current waveforms. during decoupling, the capacitor voltage suddenly increases, and the capacitor C 1 and C 2 voltages are asymmetrical. However, the output voltage did not change significantly during decoupling, so the decoupling process has little effect on the output. This is mainly because the differential mode and common mode are controlled separately, and the injection of common mode voltage does not affect the change of the differential mode component.
The curve in Fig. 14 shows that the proposed topology can increase efficiency by 5% when decoupled compared to when it is not decoupled. The topology efficiency proposed in this paper is greater than that of the traditional differential buck inverter, traditional H-bridge inverter has the lowest efficiency. In [18], the efficiency of the traditional differential buck is reduced with decoupling, so the topology proposed in this paper has an advantage in efficiency.
The efficiency of the topology in this paper is improved after decoupling, because the core loss is reduced, and the core loss is mainly positively correlated with the frequency. When the frequency is high, the core loss cannot be ignored. Therefore, the change of the core loss is mainly obtained    by observing the high-frequency harmonics in the inductor. This paper adopts the unipolar modulation mode of 10 kHz switching frequency, and the system mainly contains 10 kHz and 20 kHz high-frequency harmonics. Figure 15a shows the high-frequency harmonic distribution of the inductor before decoupling, and Fig. 15b shows the high-frequency harmonic distribution of the inductor after decoupling. The comparison shows that the content of 10 kHz harmonics is significantly reduced after decoupling, and the content of 20 kHz harmonics is almost unchanged, it can be verified that the inductor core loss is reduced after decoupling.

Conclusion
The midpoint common-mode injection topology proposed in this paper can effectively suppress the double frequency power of the system. And through theoretical analysis and experiments, we prove that the topology has the following characteristics: 1) This topology only requires the original support capacitors and filter capacitors on the DC and AC sides of the H-bridge inverter, without additional switching devices, which effectively saves costs. 2) This topology can improve the utilization of decoupling capacitors, and make the capacitors operate in positive and negative directions. Film capacitors with a lower withstand voltage can be used. 3) This topology can effectively improve the system efficiency after decoupling, and the efficiency is increased by about 5%.
The fundamental frequency common mode voltage injection is adopted, which can effectively suppress the secondary ripple on the DC side without deriving additional lowfrequency ripple, and the decoupling accuracy is high.
The follow-up will focus on improving the power density of the system, as well as research in the case of grid connection, and explore better control methods.
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