On-Chip Micro Temperature Controllers Based on Freestanding Thermoelectric Nano Films for Low-Power Electronics

Highlights Dense and flat freestanding Bi2Te3-based thermoelectric nano films were successfully fabricated by sputtering technology using a newly developed nano graphene oxide membrane as a substrate. On-chip micro temperature controllers were integrated using conventional micro-electromechanical system technology, to achieve energy-efficient temperature control for low-power electronics. The tunable equivalent thermal resistance enables an ultrahigh temperature control capability of 100 K mW−1 and an ultra-fast cooling rate exceeding 2000 K s−1, as well as excellent reliability of up to 1 million cycles. Supplementary Information The online version contains supplementary material available at 10.1007/s40820-024-01342-3.

First, the single-walled carbon nanotube (SWCNT) CNT films prepared by vacuum filtration of CNT solution were transferred onto a SiN/Si scaffold, the optical images shown in Fig. S2a, b.A commercial aqueous SWCNT suspension with an average diameter of 1.5 nm, lengths of ~15 μm and >95% purity were used (Jiangsu XFNANO Materials Tech Co., Ltd).A well-dispersed ~300 ml SWCNT suspension was obtained after 1 h ultra-sonication and 30 min centrifugation, and then was vacuum filtrated with a cellulose membrane with a pore size of 450 nm to form a CNT film, as shown in Fig. S2c, the top-view SEM image of prepared CNT film exhibits very good uniformity.Then ultra-thin hybrid membranes were prepared by pulling the CNT films from the monolayer graphene oxide (GO) solution after ultrasonic dispersion (~1 mg GO nanosheets in 10 mL deionized water, XFNANO Materials Tech Co., Ltd), which were shown in Fig. S2d (pulling process) and Fig. S2e (SEM image, showing the underlying CNTs under electron beam through ultrathin translucent GO). Figure S2f-j shows the SEM images of ~750 nm p-and n-type freestanding TE films on hybrid membranes deposited by magnetron sputtering, showing good flatness and high density.The microstructures and phase purity of the high-quality samples were characterized by XRD and SEM, and EDS were used to characterize the compositions of the samples (Figs.S2, S10 and S11).The thicknesses of the TE films were measured by cross-sectional SEM images (details in Fig. S2g, i).

S1.2 Integration process and measurement methods of TCers
The fabrication process of the on-chip TCers is shown in Fig. S1, standard MEMS process technologies were used to fabricate the suspended Si3N4 layer and multilayers of test electrodes in the device (Section 2.3 in main text).Finally, the n-and p-type freestanding TE films were integrated onto the above-prepared chips by the focused dual-beam (e/Ga) technique, including patterned cutting, transferring and bonding.C-layer deposition by e-beam before cutting and bonding by Ga-ion-beam can effectively prevent Ga ion implantation or diffusion into TE films from affecting the TE performance.In addition, the oblique cutting section is to increase the contact area to reduce contact resistance and thermal resistance.The integrated micro TE TCer is shown in the SEM image (Fig. 1e).The PPMS system can provide a high vacuum environment (~0.01 mTorr) and accurate setting ambient temperature (Ta, from 280 to 380 K, similar to the operating temperature range of microelectronics) for performance test of our -TCers.
Nano-Micro Letters S2/S17 1) Temperature and temperature difference -A Pt temperature sensor was used to assess the temperature controllability of our -TCers by monitoring its resistance value in real-time (as shown in Fig. S3a).Based on the linear relationship between the Pt resistance (RPt) and temperature (Fig. S3b), we can obtain accurate set temperature Ts (Fig. S3c) and temperature difference ΔT = Ts − Ta (Figs.S3d and 2a).
2) Cooling power -Heat-compensation method was proposed to directly test the cooling power (Pc) and coefficient of performance (COP, cooling power divided by the electrical power consumption) of our -TCer rather than the estimation based on material properties [S1-S3], in which, the key heating current I h can simulate the Joule heating effect of the micro component (heating power, Ph = I h2 × RPt) and simultaneously monitor the real-time temperature (see Fig. 1 for the schematic diagram, detailed data in Fig. S6a.For example, the relationship between the temperature control value and the two currents are shown in Fig. S6b (xz-projection of Fig. 2a) and Fig. S6c (yz-projection of Fig. 2a).Thus, by adjusting the heating power, the cooling power test under the condition of constant ΔT can be realized (Pc = Ph), including thermoelectric cooling power when ΔT is 0 K (Fig. S7a, c) based on the critical conditions shown in Fig. S6d and the cooling power under different ΔTs (Fig. S7b).
3) Thermoelectric performance of micro TE TCers -The internal resistance R can be tested in PPMS at different ambient temperatures Ta.In addition, the voltage V of the Pt sensor and Seebeck voltage Us of the μ-TCer as a function of Ih could be tested (Fig. S6e), as well as corresponding heating power (Ph = V × Ih) and ΔT = Ts − Ta (Fig. S6f, g).The approximately linear relationship of P h and Us with ΔT can be used for calculating the thermal resistance (Rth = ΔT / P h), and device Seebeck coefficient (α = Us / ΔT) , which includes the Seebeck coefficient of a pair of the P-and N-type thermoelectric legs, ( =  P −  N) of the μ-TCer, respectively, detailed data are shown in Fig. 3.

4)
Efficiency measurement -The COP can be obtained by dividing the Pc by the power consumption (P), as shown in Fig. S7d, e.Note that power consumption can be obtained by calculating, P = (I w simulated power electronics (Fig. 4) based on the detailed data in Fig. S8.When Ts is set as 360 K, based on the curve of P with Ta (Fig. S8e), the calculated average power consumption P ̅ is only ~32 μW after avoiding overcooling and overheating (Fig. S8f).

Section S2 Conductive Heat Loss through the Pt Sensor
Basically, the S/L value directly affects the internal resistance R and thermal resistance Rth of the TE legs, and therefore indirectly affects the total internal resistance Rtot = R + Rin (R and interface resistance R in are in series) and total thermal resistance R th tot = Rth + R th in (Rth and interface thermal resistance R th in are in series) of the TE devices (Tables S1 and S2).
In the out-of-plane film TE device, since the S/L value is relatively large compared with in-plane films (Table S3), the proportion λ1 = R/Rtot and λ2 = Rth/R th tot are not high enough.In order to reduce the adverse effects of Rin and R th in by increasing λ1 and λ2 valves, Rth and R can be increased by extending the L value (or reducing S/L), which can increase the cooling temperature difference Tc (ref.[S4]).When L increases and the proportion λ is close to 100%, the theoretical maximum Tc (T c0 max ) could be achieved, which is then mainly determined by TE properties if there is no other heat loss.
On the contrary, the S/L values of our in-plane films are already very small (two orders of magnitude lower than the out-of-plane films, see Table S3), and λ should be close to 100%.For only TE legs, the relationship between cooling power Pc with T c0 max and Gth (thermal conductance Gth = Nano-Micro Letters S3/S17 1/Rth) can be approximately expressed as: Pc = Gth ×T c0 max .Then when considering the conductive heat loss through the Pt sensor (its Gth* is in parallel with Gth).Therefore, Pc = G th tot × T c max and T c max = (T c0 max × Gth)/(Gth + Gth*), details in Table S2.As a result, the factors that actually affect the T c max are the heat loss (Gth*) and the S/L value since Gth is linear with the S/L value.The conductive heat loss through the Pt sensor is the main reason why Tc increases with the increasing S/L value (Fig. 2b).
To further verify the above results, we performed Finite Element Simulation using the COMSOL Multiphysics software.The device design parameters and materials properties can be found in Tables S1 and S2 and Fig. S5.First, the thermal conductivities (κ) of the thermoelectric thin films are calculated using the Wiedemann-Franz law (κ = LT + κl), the Lorenz number L = 2.4×10 −8 V 2 K −2 (ref.[S5]), the electric conductivity () as a function of absolute temperature (T) can be found in Fig. S5.To match the thermal resistance value R th tot of TCer in Fig. 3d, the lattice thermal conductivity (κl) is set as 0.45 (0.4) W m −1 K −1 for p (n)-type film.And considering the influence of the interface effect, the tuning factor F (defined as the ratio of the performance used in device simulation to the material performance), F1 = 0.8, F2 = 0.9 and F3 = 0.9 are used for the Seebeck coefficient, electric and thermal conductivities, respectively.The simulation results are shown in Fig. S4, the maximum cooling temperature difference increases but the rate of increase gradually decreases with the increase of the S/L valve.These results directly indicate that conductive heat loss is an important factor affecting the cooling temperature difference.The calculated heat loss ratios data of each device are shown in Table S2.

Section S3 Cooling Performance Comparison
From the viewpoint of application for microsystem temperature control, one of the advantages of micro thin-film (out-of-plane and in-plane) TECs (http://www.lairdtech.com) is that they feature higher cooling power density compared to bulk TECs (https://rmtltd.ru)and are therefore considered to be more suitable for thermal management of microsystems.The ultra-high Rth of our -TCer is ~345 K mW −1 , which is two orders of magnitude higher than that of the out-of-plane TECs due to the smaller S/L of our TE legs, and also higher than that of non-freestanding in-plane TECs by avoiding heat loss from the substrates (Fig. 2c and Tables S1 and S3), making its temperature control capability  extremely high (Fig. S8d).The  values are several orders of magnitude higher than those of conventional TECs and microheaters [6], exceeding 100 K mW −1 even under the maximum cooling temperature ΔT c max .The  values of our -TCers increase significantly with increasing Rth (with decreasing S/L value from NO.7 to NO.1 and/or ambient temperature from 380 K to 300 K), which are shown in Fig. 2c.Therefore, we can conclude that large Rth is extremely important for energyefficient temperature control.In addition, the achievable cooling temperature differences of our inplane -TCers are much higher than those of previously reported in-plane TECs, and comparable to the best out-of-plane superlattice-based TECs (details in Tables S1 and S3).We compared the ΔT c max and the maximum cooling power P c max values of our -TCer with those of traditional thin-film TECs in Fig. S13.While the cooling power of in-plane TECs is only sub-mW much lower than that of outof-plane devices due to the extremely small cross-sectional area, which makes the former more suitable for low-power micro components, and the latter for high-power devices in thermal management.

Section S4 Convective and Radiative Heat Loss
Figure S12 shows that increasing working pressure results in a non-negligible heat loss power PL through air convection, ultimately leading to a 95% reduction in ΔT c at atmospheric pressure.Even when the pressure decreases to ~7 Torr, the ΔT c and heat loss values also change rapidly, which indicates that heat transfer at the solid-gas interface is comparable to the heat conduction through TE legs.The performance of the microheater [S7] and microfluidic calorimeter [S8] are also sensitive to Nano-Micro Letters S4/S17 this Torr-scale pressure.Fortunately, vacuum packaging can meet the working pressure requirement, the performance reduction is less than 0.5% in an industrial 10-mTorr vacuum [S9].S13 Comparison of the cooling performance of previously reported micro TE coolers, including the maximum cooling temperature difference ΔT c max (cooling power is zero) and the maximum cooling power ΔP c max (ΔT is zero) of unicouple TEC (one pair of TE legs).The area sizes of the blue bubbles outside the symbols reflect their cooling power density Q c .Corresponding thermal resistances for these one-pair TE legs are also indicated.Details, full references and further performance are provided in Tables S1 and S3 10 -2 10 0 10 2 10 4 10 6

FigFigFig
Fig. S8 Power and efficiency

Table S1 |
Table of all design parameters and performance of TE TCers *** All cooling performance at 380 K (in PPMS system).

Table S3 |
Selected references for the comparison of TECs used in Fig.2c # All cooling performance for unicouple devices unless otherwise specified.* Single leg device.*