Fuzzy Hold Flip-Flop and Flip-Flops Hardware Realizations

This paper presents a new type Hold (H) of two-input fuzzy flip-flops. The definition of fuzzy H flip-flop for different fuzzy operations is given, the characteristics presented and selected properties pointed out. The new flip-flop is compared with other two-input fuzzy flip-flops described in the literature. Moreover, the potential for hardware implementation of fuzzy flip-flops is analyzed and diagrams, with the use of standard digital blocks, given. Special attention is paid to Lukasiewicz fuzzy flip-flops which allow efficient hardware realization. After the identification of the essential features of FPGAs, the presented diagrams were implemented in a Spartan-6 device. This allows the assessment of the suitability of FPGAs for fuzzy flip-flop implementations, as well as reception of fast and area optimized fuzzy flip-flops.


Introduction
For many years, fuzzy flip-flops have been considered a replacement for binary flip-flops in fuzzy systems, acting as primary storage elements. The concept of a fuzzy flip-flop was presented by Hirota and Ozawa in [7]. Generalizing a binary JK flip-flop by replacing the logical conjunction, disjunction and negation, respectively, with t-norm, s-norm (t-conorm) and fuzzy negation they received the fuzzy flipflop. Fuzzy operations do not hold distributive lows, the non-contradiction low and the excluded middle low, so that minterm and maxterm forms of fuzzy flip-flops characteristic equations, derived from binary flip-flops, are not the same (in contrast to binary flip-flops). This in turn initiated the search for characteristic equations of fuzzy flip-flops which ensure the identity of characteristics and enable convenient implementation in integrated circuits.
The equation of the first fuzzy JK flip-flop, based on Zadeh (min-max) operations, and its implementation were shown in [7]. An algebraic JK flip-flop was described in [11]. In [3], the authors made an attempt to specify a bounded JK flip-flop. In [5], a lack of analogy of this flipflop to binary flip-flop for K ¼ 0 and J ¼ 0 was stated, and a family of four JK flip-flops JK SA , JK AA , JK AB and JK SB was proposed.
After the JK flip-flop, other flip-flops were also fuzzified. The definition of fuzzy SR flip-flop can be found, among others, in [1,6,15]. Due to the forbidden state when S ¼ R ¼ 1, fuzzy SR flip-flop was developed in two types, Set and Reset [15].
This article briefly describes the characteristic equations of binary and fuzzy flip-flops, covered so far in the literature. Against this background, we introduce a new fuzzy H (Hold) flip-flop. The characteristic table and the definition with characteristic equations will be given, selected properties discussed and characteristics illustrated. Diagrams of Zadeh and bounded fuzzy flip-flops using standard digital blocks will also be depicted. Next, the implementation of the diagrams in the Spartan-6 FPGA XC6SLX16 device will be presented. The implementation was preceded by the indication of properties of FPGA structure, which will have a significant impact on the final results. This, in conjunction with an analysis of characteristic equations of Lukasiewicz flip-flops, allowed us to get fuzzy flip-flops with very good timing performance and also occupied a very small area.

Binary Flip-Flops
In most cases, binary flip-flops are the basis for development of fuzzy flip-flops. In digital systems, commonly used two-input binary flip-flops are JK and SR flip-flops. The characteristic table of these flip-flops is presented in Table 1.
Q is the current state of the flip-flop and Q þ is the next state. In order to compare the characteristic table of different flip-flops, the inputs in Table 1 are marked twice.
The JK flip-flop has inputs called J and K. A high state at J while K is held low sets the output high, and a high state at K while J is held low resets the output. When J ¼ K ¼ 0, the flip-flop remembers a previous state, and when J ¼ K ¼ 1 it changes its state to opposite. JK flipflop characteristic equations, describing its next output state Q þ , in the form of sum of products give Eq. (1) and in the form of product of sums Eq. (2) 3 Fuzzy Flip-Flops A common practice for developing fuzzy flip-flops is to generalize binary flip-flop characteristic equations by fuzzy norms. Popular operations used as fuzzy norms are Zadeh-min-max (^, _), Lukasiewicz-bounded (, È), algebraic and drastic operations with a complement (A ¼ 1 À A) as a fuzzy negation [7,16]. More complex operations, e.g., Yager, Hamacher, Dombi, Dubois-Prade and Frank, cause a lot of problems in hardware implementation and are rarely used (especially in simulations). Despite the fact that some of fuzzy triples hold De Morgan laws, none of them holds either distributive lows, the noncontradiction low and the excluded middle low. This causes that the minterm and maxterm forms of generalized Eqs. (1)(2)(3)(4) are not the same. Moreover, a generalized JK flip-flop does not meet the boundary value specified in Table 1 [7]. To fulfill boundary demands and integrate minterm and maxterm characteristic, the authors modified the characteristics equations of fuzzy flip-flops. The first fuzzy flip-flop was Zadeh (min-max) JK flip-flop with the characteristic equation (5) defined in [7]. The same flip-flop with algebraic operations was described in [11] by the characteristic equation (6) Q The bounded fuzzy JK flip-flop with Eq. (7) was presented in [3]. While K ¼ 0 or J ¼ 0, the bounded value of this flip-flop does not retain the analogy with a binary JK flop-flop. In [5], a family of four flip-flops JK SA (8), JK AA (9), JK AB (10) and JK SB (11) which provides such an analogy was proposed. where where The Lukasiewicz JK flip-flop can also be described by Eq. (12) where This equation provides the most similar characteristic to Lukasiewicz Set-type and Reset-type JK flip-flops, which comes directly from generalized minterm and maxterm forms of a binary JK flip-flop. JK SA (8) and JK AA (9) flip-flops do not achieve a symmetry of characteristics which have Zadeh (5) and algebraic (6) flip-flop. Equations (10-12) allow the achievement of such a symmetry; however, they are complicated and therefore inconvenient for hardware implementation.
The forbidden state, occurring in a binary SR flip-flop when S ¼ R ¼ 1, is not desirable for fuzzy flip-flops. It will eliminate a large range of input values, which simultaneously partially belong to a high state. Therefore, fuzzy SR flip-flops are available in two types: Set and Reset. Table 2 lists the characteristic tables of two-input fuzzy flip-flops.If S ¼ R ¼ 1, the next state of a Set-type fuzzy SR flip-flop is high and a Reset-type is low. In this inputs configuration, the JK flip-flop takes the next state of Q.
Set-type and Reset-type fuzzy SR flip-flops with various fuzzy operations were discussed in [6,15]. The characteristic equation of the Set-type fuzzy flip-flop was defined as and the Reset-type as

The Fuzzy H Flip-Flop
The general definition of a fuzzy H flip-flop is given in Definition 1.

Definition 1
The fuzzy H (Hold) flip-flop has two fuzzy inputs S and R and a fuzzy output Q, reflecting its actual inner state. A high state at the S input sets the output Q high and a high at R resets the output. If inputs are S ¼ R ¼ 0 or S ¼ R ¼ 1, this flip-flop holds the output at the previous state Q.
In Table 2, the characteristic table of a Equations (15) and (16) are derived, respectively, from Set-type and Reset-type fuzzy SR flip-flops, but in contrast to them, they satisfied Theorem 1. (15) and (16) for Zadeh and Lukasiewicz operations are identical.
Equations (21) and (25) result in (26) which ends the proof. h The equation of algebraic H flip-flop determines Definition 3.

Definition 3 The algebraic fuzzy H flip-flop is described by the characteristic equation (27)
Characteristics of the next state Q þ H of a Zadeh H flip-flop for different values of previous state Q are shown in Fig. 1. The characteristics confirm that for all value of Q Zadeh H flip-flop meets the requirements specified in Table 2 which is independent of initial or actual state and depends only on the inputs S and R. Previous Q is held when S ¼ A fuzzy H flip-flops allow the building of fuzzy register. A Zadeh and a Lukasiewicz H flip-flop also permit to easily build fuzzy shift register (Fig. 7). In a Zadeh shift register, H flip-flops catch actual input state when R ¼ S (Fig. 6). Lukasiewicz H flip-flops transfer input S to the output when R ¼ Q as a result of calculation An example of binary H flip-flop diagram is shown in Fig. 8. The gray area is an H latch. The rising edge of clock C blocks the latch and transfers its state to the output Q. The falling edge of C unblocks the latch and actives the output loop. Fuzzy H flip-flops, together with a binary H, allow the construction of a mixed fuzzy-binary system.   The following part of the paper discusses the realization of Zadeh and Lukasiewicz discrete flip-flops. Flip-flops are ended with synchronous elements.

Zadeh Fuzzy Flip-Flops
Zadeh operations can be made using a comparator and a multiplexer. In Fig. 9, diagrams of Zadeh (a) t-norm and (b) s-norm are presented . The diagrams differ in connections of multiplexer inputs. For the construction of these operations, the n-bit comparator and n of 2:1 multiplexers are used. Similar realizations of Zadeh operations, using comparators and multiplexers, are presented, e.g., in [8,12].
With  16), is presented in Fig. 11. The number of digital blocks required to build Zadeh fuzzy flip-flops is collected in Table 3. The least amount of elements requires SR flip-flops and the most JK flip-flops.

Lukasiewicz Fuzzy Flip-Flops
Lukasiewicz operation diagrams are usually based on a carry adder with an additional element in the output, imposing an appropriate limitation on its value. To restrict the output value, we can use logic gates [3], multiplexers [9,16] or Set/Reset input of synchronous elements [14].
Diagrams of Lukasiewicz (a) t-norm and (b) s-norm with gates at the output are shown in Fig. 12. In the case of t-norm, the CI input of the adder is connected to a high state. If the CO output of the adder is low (A þ B þ 1 2 1), then the output of the circuit is also held low by AND gates. A high state in the CO output (A þ B þ 1 2 [ 1) causes the circuit to perform operation by omitting the most significant bit of the sum (carry bit CO).
In the case of s-norm, a sum A þ B is transmitted to the output until a high state of CO output of the adder (A þ B [ 1). A high state at the CO, through OR gates, holds the output in a high state.    Lukasiewicz operations with multiplexers work in the same way, and their diagrams are presented in Fig. 13. Multiplexers, controlled by the CO output of the adder, switch t-norm state between 0 and A þ B À 1, and s-norm state between A þ B and 1. Diagrams of Lukasiewicz operations with synchronous elements (D flip-flops) are illustrated in Fig. 14. Considering the s-norm, a high state of the carry CO, connected to the S (Set) flip-flop input, sets the output high. In the case of t-norm, the carry CO is connected through an inverter to the input R (Reset). As a result, a low state of CO resets the flip-flop.
The number of digital components required for construction of presented diagrams of fuzzy Lukasiewicz operations is summarized in Table 4.
Diagrams of Set-type and Reset-type fuzzy SR flip-flops can be obtained using discussed realizations of Lukasiewicz operations and the characteristic equations (13) and (14). Equation (13) is reflected by the diagram presented in Fig. 15. The operation R Q is composed of the adder with AND gates (Fig. 12a), while the Lukasiewicz sum, due to the requirement of synchronous fuzzy flip-flop output, consists of the adder and binary flip-flops (Fig. 14b). By analogy, the diagram of a Reset-type flipflop [Eq. (14)] is shown in Fig. 16.
Equation (20), which is the extension of the characteristic equation of a Set-type fuzzy SR flip-flop (Eq. (13)), can also be written as Equation (32) corresponds to the diagram presented in Fig. 17. Multiplexers are driven by a signal CO 1 of the first adder. When CO 1 ¼ 0, multiplexers provide the input of D flip-flops with a signal S. If CO 1 ¼ 1, the first adder produces a signal Y r À 1 ð Þ, and the sum Y r À 1 ð ÞþS from the second adder feeds D flip-flops. If carry signals CO 1 and CO 2 are held high then the AND gate, connected to S input of flip-flops, sets the state 1 at its output.
Similarly, from Eq. (24), describing a Reset-type fuzzy SR flip-flop, written in the form of we can obtain the diagram presented in Fig. 18. In this case, D flip-flops are reset at low state of CO 1 and CO 2 . If CO 1 ¼ 0 and CO 2 ¼ 1, the first adder produces a sum Y s and the second adder performs operation (31). While CO 1 ¼ 1, the signal R feeds D flip-flops. Based on the characteristic equations (15) and (16) of the H fuzzy flip-  flop, which contain four fuzzy operations, it could be deduced that its diagram will be twice the size of the SR flip-flop. However, analyzing the values taken by the flipflop, its diagram can be simplified. Equation (21) can be written as Equation (34) allows to obtain the diagram of the H fuzzy flip-flop presented in Fig. 19.Depending on the condition Y r [ 1, operation (31) is performed in the first or in the second adder. The boundary of a state 1 imposes the AND gate at CO 1 ¼ CO 2 ¼ 1, and relating to the state 0 the NOR gate at CO 1 ¼ 0 and CO 2 ¼ 0. Similarly, Eq. (25) in the form  adder will be fed by a signal S and which by R. There is also no difference whether CI 1 ¼ 0 and CI 2 ¼ 1, or CI 1 ¼ 1 and CI 2 ¼ 0. Table 5 summarizes the number of components used to build presented Lukasiewicz flip-flops.The least amount of digital elements requires an H flip-flop. Its construction, in addition to two n-bit adders, inverters and flip-flops, also used in all other diagrams, needs one two-input AND gate and one NOR gate.
where p i ¼ a i XOR b i is produced in a LUT (lookup table). The a i and b i are, respectively, the ith bits of input fuzzy numbers A and B. The carry bits c i are generated by multiplexers MUXCY. Multiplexers MUXCY can calculate conjunction a i b i as and it is required to supply a signal a i or b i or their logical product. During implementation, attention has to be paid to several important properties of the Spartan-6 slice structure.
Property 1 D flip-flops are directly after XOR gates. Therefore, if in Lukasiewicz flip-flop diagrams D flip-flops occur immediately after the adder (Figs. 15, 16, 19, 20), it  Property 3 Additional resources are also required by the logic gates, which bound the output value based on carry signal from adders. These gates often build a critical time path; thus, their performance determines the maximum operating frequency of the whole fuzzy flip-flop. The best way to realize the inverter (Fig. 16), the XOR gate (Fig. 22 instead of OR gate) and the AND gate (Figs. 17, 19, 20) is to use the components of carry logic which are associated with the second adder carry chain. Timing simulations have indicated that the inverter implemented in a XORCY gate in the form of CI 2 ¼ CI 2 XOR 1 ð Þ significantly affects the maximum operating frequency (in the case of the 4-bit Lukasiewicz flip-flop, the maximum frequency has increased from 164.962 MHz to 225.023 MHz). The AND gate can be the product of a multiplexer MUXCY configured according to equation CI 1 CI 2 ¼ CI 1 CI 2 þ CI 1 0. On the other hand, both OR and NOR gates can not be created in such an effective way.
Property 4 LUTs, calculating propagation group p i , allow to implement one arbitrary six-input logic function or two five-input logic functions which share the same inputs. The O5 output can also supply an input of MUXCY multiplexer. As a result, logic elements on inputs of Lukasiewicz flip-flop adders can be done in LUT tables calculating propagation group. Thence, logic elements on adder inputs will not have a significant impact on the occupied area and timing performance. In the case of the H flip-flop from Fig. 22, two-output LUTs also permit to place AND gates (of the Reset circuit) and D flip-flops in the area of the second adder. This can be done by looping the signal from the second adder to its subsequent input of LUTs and producing on their O5 outputs AND gates. Such action significantly reduces the occupied area by H flipflop, but additional delays, caused by the loop, have to be reckoned with.
Taking into account the discussed properties, the best implementation results, in terms of both occupied resources and the maximum clock frequency, are expected for the Set-type SR flip-flop (Fig. 15). In this fuzzy flip-flop, according to Property 1, D flip-flop comes right after an adder, only the Set input is used (Property 2) to which is applied a signal CO 2 without additional gates (Property 3), and all logic gates can be integrated with adders (Property 4). Table 6 Summary of three fuzzy flip-flop implementation in Spartan-6 FPGA (Fig. 23) 7 The Results of Implementation in FPGA Comparison of fuzzy flip-flop FPGA implementation results was performed as follows. Zadeh and Lukasiewicz fuzzy flip-flops were coded behaviorally in VHDL. In order to fulfill the requirements stated in Sect. 6, Lukasiewicz flip-flops were additionally described structurally. In structural descriptions, primitives of Xilinx FPGA device components (LUTs, XORCY gate, MUXCY multiplexer and D flip-flop) were used. Components were properly distributed with the use of RLOC attributes. Details of fuzzy operations structural description can be found in [14]. The Xilinx Spartan-6 FPGA XC6SLX16 was selected as the target device, mounted on an inexpensive evaluation kit SP601. In this device, three flip-flops connected as shown in Fig. 23 were implemented.This diagram allows the area occupied by three fuzzy flip-flops and their maximum clock frequency (associated with the delay produced by combinatorial logic placed between synchronous elements) to be determined. A timing constraint of 200 MHz was imposed on the clock frequency. During synthesis and implementation, the design goal was timing performance. The occupied area was taken from the Place and Route Report, and the maximum operating frequency came from the Post-PAR Static Timing Report. Table 6 summarizes the implementation results.
Considering the occupied area, the best results for all tested bit resolutions were obtained for structural descriptions of a Lukasiewicz Set-type SR flip-flop. Their area was equal to the resources of two adders. Three 4-bit flip-flops took a total area of 6 slices (2 slices per flip-flop). A slightly worse result was achieved for other bounded flipflops described structurally. It is connected with the implementation of flip-flop boundaries logic. Behavioral description outcomes were far worse than structural ones. Among them, most of the flip-flops with the same resolution took a similar area. Significantly lower resources than the average were required for the behavioral description of a 4-bit Zadeh Set-type SR flip-flop. This flip-flop also reached the highest clock frequency of all tested flip-flops. Unfortunately, for other resolutions the outcome was much worse. The worst results gave a Zadeh JK flip-flop. It occupied the largest area and had the worst timing characteristics. Zadeh H flip-flops had also poor performance. It is worth to point out that the area of Zadeh flip-flops shrank from 8-bit to 12-bit implementation. The reason was that the synthesizer in 12-bit and 16-bit implementations used MUXCY multiplexers.
Comparing the maximum clock frequency, it is noticeable that the frequency decreased very fast in the case of Zadeh flip-flops. In Lukasiewicz flip-flops, both described behaviorally and structurally, and this decline was much slower. Although the 4-bit Zadeh Set-type SR flip-flop reached the highest clock frequency, bounded flipflops performances outweighed Zadeh flip-flops at 8-bit resolution and higher. Structurally described flip-flops, with the properties listed in Sect. 6, got a high clock frequency compared to other flip-flops. In this case, like in the case of the occupied area, the best results were obtained by the Set-type SR flip-flop. Good results were also achieved by H flip-flops, despite the fact that the structure of FPGAs does not exactly fit to Figs. 19 and 20. The lowest clock frequency had JK flip-flops.

Conclusion
The paper presents a new type H (Hold) of fuzzy flip-flop. Its definition, characteristic equations and selected properties were covered. The characteristics of this flip-flop with a variety of fuzzy operations are similar but more homogeneous then corresponding JK and SR flip-flops. Moreover, fuzzy H flip-flops can easily be used in many applications starting from fuzzy register or shift register to more sophisticated like neural nets, fuzzy Petri nets or fuzzy-binary system. The article also presents schematics of Zadeh and Lukasiewicz fuzzy flip-flops. Despite more complex characteristic equations, the Lukasiewicz H flipflop demands the smallest number of digital blocks. On the other hand, the implementation of fuzzy flip-flops in the FPGA showed that the best fitted to the structure of FPGAs is the Lukasiewicz Set-type SR flip-flop. Nevertheless, with a structural description Lukasiewicz flip-flops with a small area and high timing performance can be obtained.
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