Quantum analytical modeling and simulation of CNT on insulator (COI) and CNT on nothing (CON) FET: a comparative analysis

A comprehensive performance analysis by quantum analytical modeling of CNT on insulator (COI) and CNT on nothing (CON) FET having channel length 20 nm has been proposed and investigated on the basis of 2D Poisson’s Equation and solution of 1-D Schrodinger’s Equation and validated using ATLAS 2D simulator. As classical approximations fail to describe carrier quantization, charge inversion and potential profile of a device at sub-100 nm regime, here for the first time an analytical model in quantum mechanical aspect for COI/CON devices has been derived. Effects of high-k dielectrics in place of conventional SiO2 over the device characteristics have been thoroughly discussed. Moreover, all noticeable benefits of our device to the so called SOI/SON architecture have also been vividly justified.


Introduction
VLSI/ULSI industry is continually being grown up over the platform of rigorous downsizing of devices [1]. This needed an optimization between ultra high speed and ultra low power consumption in making denser circuits [2][3][4][5][6]. But lowering dimensions indeed lowers the control of gate over the channel as lateral electric field turns to be significantly larger than the vertical electric field which in consequence invokes degradation of device performance including DIBL, gate tunnelling, threshold voltage roll-off, hot carrier effect [2][3][4][5]7] etc. Therefore to suppress those undesired phenomena as well as to design the device in such away it can operate faster, researchers moved forward with the discovery of non-classical structures. Fully depleted silicon on insulator (FDSOI) was a device [6] with buried oxide layer to minimize electrostatic coupling, better subthreshold behaviour, and reduced junction capacitance gaining higher speed of operation. But FDSOI [2,3] suffered a lot from accumulation of positive charges at the buried layer. That is why a little rectification was done to the device structure by replacing thick oxide with embedded air gap to form silicon on nothing (SON) MOSFET [2,5,8] keeping all the advantages of SOI structure unaffected.
In our present work, we have designed an implanted CNT channel on weakly inverted SOI and SON devices for higher speed of operation, diminishing SCE and improved subthreshold characteristics. From the very invention in 1991 by S. Iijima [9], CNT being a rolled graphite sheet in tubular form [10][11][12][13][14][15][16] originating Quasi-1 dimensional approach [17,18] in nano-science has been considered attractive by scientists to be used in non-classical devices as it holds exceptional mechanical and electrical properties [9,18] like very high tensile strength, high flexibility and elasticity, low thermal expansion coefficient, high electrical conductivity and can be found with significantly high aspect ratio. Conductivity of CNT sincerely depends upon its chirality [17,18], diameter of nanotube and degree of twist [10]. Having strong carbon-carbon bond in the planar honeycomb structure of graphite [9], the modulus of elasticity at its basal plane is superior than most of the materials known has proved itself trustworthy as per their fabrication is concerned. Near ballistic transport [14,15] of mobile carriers through the CNT channel can be observed with the absence of dangling bonds. In this paper, keeping channel length 20 nm and taking diameter of nanotube 1.5 nm for optimum transport, we have analytically modeled COI/CON devices [19] influenced with quantum mechanical [16,[20][21][22][23] effects as dimensions can be compared with the De-Broglie wavelength. Novelty of this paper lies on simplicity of our mathematical model for most of the general characteristics of COI/CON devices.
Device structure Figure 1 schematically shows the cross sectional view of weakly inverted carbon-nanotube on insulator (WICOI) or carbon-nanotube on nothing (WICON) FET. Here source and drain are heavily doped where semiconducting zigzag CNT channel [18] is lightly doped. t f , t cnt , t ox/air , and t sub are front gate oxide thickness, thickness of channel, buried oxide/air gap thickness and substrate thickness, respectively. 'L' is defined as channel length. Contacts are provided with voltages accordingly.

Analytical model
As potential distribution along the channel is absolutely two dimensional in nature for this kind of devices, Poisson's Equation can be applied [8,15] at CNT channel along its length and thickness. Assuming comparable acceptor and hole concentration for zigzag (n, 0) CNT, the normalized density of states per unit length can be expressed as [17]: for total number of states between E and E þ oE where E can be E cb E E ct for conduction band and E vb E E vt for valance band implying 'b' and 't' suffixes are used to define bottom and top of the band. Again, E vh1 and E vh2 being Van Hove Singularity [9][10][11][12][13][14][15][16][17][18]24] energies where DOS is real and finite to be: Now band gap is determined with the expression: =p and a cc is carbon-carbon length &1.42 Å . Therefore, hole concentration can be written with valance band DOS [17] as: If drain to source voltage is kept low, dependence of potential on lateral direction can be parabolic in nature and expressed as: is the surface potential, C1ðyÞ and C2ðyÞ are arbitrary and functions of y only. Y and X are considered as horizontal and vertical positional coordinates. If eox=air is the dielectric constant of oxide/air implantation, / f ðyÞ and / b y ð Þ stands for front side oxide-CNT interface and back side CNT-oxide/air interface so that / f ðyÞ ¼ / 0; y ð Þ and / b y ð Þ ¼ / t cnt ; y ð Þ. Moreover, tf is the gate oxide thickness and t ox=air is the buried oxide/air gap thickness. Coefficients and other variables can be found in detail at Appendix: [A].

Surface potential
Now these constants are put on Poisson's Equation and using the parabolic approximation, we get expression of surface potential as:

Electric field
The lateral electric field can be obtained by differentiating the surface potential with respect to y:

Subthreshold Slope
To calculate the subthreshold slope following equation must be taken under consideration: where expression for o/ f y ð Þ oV gs and / f min y ð Þ are shown in detail at Appendix: [B].
Moreover, dependency of y 0 over / bi is also taken care of.

Classical threshold voltage model
As threshold voltage is the value of gate to source voltage for which, where V T is the thermal voltage and n i is intrinsic doping concentration, then classical part of threshold voltage can be found as: Appendix: [C], different parameters like A, B, C, D, P, T and m, as used in Eq. (5), are defined.

Formulation of inversion charge and quantum threshold voltage model
Carrying out investigation over inversion charge along the channel, first the nature of potential well is to be determined. We found it 'Triangular' as depicted in Fig. 2. Now total threshold voltage can be derived as V q th ¼ V cl th þ DV q th . Shift of quantum threshold voltage [8] can be derived to be:

Results and discussion
WICOI/WICON structure with gate oxide thickness, t f to be 2 nm, channel thickness, t cnt 1.5 nm, source/drain doping of 5 9 10 24 m -3 , Effective mass of electron 0.053 9 9.1 9 10 -31 is considered here for mathematical model as well as for simulation with ATLAS-2D simulator to validate the model. Semiconducting zigzag CNT (19, 0) of diameter 1.5 nm has been taken as channel material having carbon-carbon length of 1.42 Å , nearest neighbour overlap energy being 2.7 eV and band gap of 0.51 eV. Figure 3 shows asymmetric surface potential distribution for gate to source voltage 0.2 V and drain to source voltage 0.35 V. Shift of minima of the potential parabola towards source side is the consequence of different channel potential. The downward shift of the minima for CON structure implies better immunity to common SCE's and DIBL also. Figure 4 tells us about the effect of change in the permittivity of gate dielectric as channel length downsizes from 200 nm. Application of high-k material simply creates higher value of C f contributing to lower surface potential for both COI and CON devices.  Electric field, as found in Fig. 5, increases gradually towards drain with small negative initial values at source side. At middle of the channel, electric field for COI places more downward deviation than CON justifying better carrier transport for CON devices. Figure 6 is about comparison of subthreshold slope where CON experiences lower slope value than COI due to its reduced front to back potential coupling ratio. Figure 7 expresses the variation of quantum threshold voltage shift along the channel differed by device structure where COI has relatively steep fall than CON device signifying less effect of channel length variation over CON. Figure 8 defines the effect of high-k dielectric to vary quantum threshold voltage on COI/CON device. Threshold voltage drop is more with the application of low-k material as gate dielectric, making it prone to undesired performance complications. Figure 9 depicts the reduction in quantum threshold voltage shift with increment of channel thickness. This can be elucidated as potential-well previously formed, experiences increment when diameter of implanted CNT is of higher value. Relaxation of quantized nature occurs gradually in terms of increased channel thickness as separation of any two energy levels possesses minimum value. Figure 10 is of true importance as it justifies CON to possess immense improvement over SOI, SON and COI as per DIBL is concerned. Here DIBL is calculated in terms of the difference between linear and saturation threshold

Conclusion
Present analysis reveals most of the performance related characteristics of COI/CON structure being sincerely considered for modeling in quantum mechanical aspect. Quantum threshold voltage has been successfully derived on the basis of the formation of inversion charge as well as quantum wells with discrete energy levels. Proposed model has its ultimate immunity against major SCE's including DIBL as validated with good agreement with the data found by ATLAS in ''Results and discussion''. Reduced subthreshold slope implying strong gate to channel coupling with application of high-k gate dielectric recommends the device to fulfil the ever increasing demand of nano-technological industry today. This structure, if fabricated precisely, can be implemented in device-circuit mutual integration platform to deliver ultra-high speed with its nearly ballistic transport. Moreover, this simple model can further be improvised with the application of pocket implantation and work function engineered binary metal alloy gate as future scopes.
Acknowledgments The work has been supported by UGC_UPE phase-II with Ref. No: R-11/43/2013. The authors also thankfully acknowledge the valuable technical discussions with Gargee Bhattacharyya.
Open Access This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://crea tivecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

Appendix: [A]
Coefficients are: to be front channel oxide capacitance and C ox=air ¼ e ox=air t ox=air to be back channel oxide/air capacitance.

Appendix: [B]
In determining Similarly, Here, y 0 is undoubtedly, position in the channel where surface potential is minimum and if J = L 2 þ 1 2 ffiffiffi S f p then it is obtained as: Now, to find the classical threshold voltage, we assume . This makes simply understandable classical threshold voltage.

Appendix: [D]
Schrodinger's equation can be solved for triangular potential well which is given by: F can be treated as electric field across film thickness. At surface, (8) can invoke quantized energy levels as: Now, critical charge is derived with the help of Boltzmann's Statistics as: , which can be simplified as: with the help of fermi-dirac distribution, total inversion charge per unit valley becomes as: