Stacked Lateral Gate-All-Around Metal–Oxide–Semiconductor Field-Effect Transistors and Their Three-Dimensional Integrated Circuits

According to the International Roadmap for Devices and Systems, gate-all-around (GAA, also known as a surrounding gate) metal–oxide–semiconductor field-effect transistor (MOSFET) will be the main device in integrated circuits (ICs). Lateral GAA (LGAA) MOSFETs have been applied in CMOS logic circuits from a 3-nm technology node. However, further shrinkage of the contacted gate pitch is difficult owing to the physics and processing limitations. Three-dimensional (3D) stacking of chips or wafers is therefore widely studied for high integration. However, the device distance between stacked chips or wafers is rarely less than 10 µm, which is too long considering the electrical resistance and transfer delay, especially for logic circuits. Complementary field-effect transistors are currently a widely used 3D logic device; however, a compatible process is required for the heterostructures. The authors previously developed a fabrication process for symmetric-source/drain vertical GAA (referred to as ultimate VGAA, UVGAA) MOSFET for the first time; a novel architectural 3D IC with stacking UVGAA-based devices (CMOS and/or SRAM) in the vertical direction was also developed. In this perspective, a fabrication process for stacked LGAA (SLGAA) MOSFETs in the vertical direction is proposed for the first time and a high integration 3D logic IC based on SLGAA MOSFETs is also developed. These novel 3D architectures lay the foundations for next-generation ICs.


Introduction
High integration (density), high speed, and low energy loss are principal targets for integrated circuits (ICs). These targets result in the fact that Silicon (Si) is the primary material for the semiconductor industry owing to its outstanding properties for devices and processes. Metal-oxide-semiconductor field-effect transistors (MOSFETs) are the key devices for ICs. MOSFET miniaturization is guided by Moore's law for more than 50 years and has had significant benefits on ICs. However, the miniaturization of Si-based MOSFETs to nanometer level leads to some unfavorable characteristics, such as the short-channel effect, which increases the energy loss of ICs. Furthermore, miniaturization has achieved physical and processing limitations; thus, further shrinkage of the contacted gate pitch below a 7-nm technology node is difficult. That is, it is difficult to further increase integration. The "Beyond CMOS," which focuses on the emerging architectures, emerging devices and processes, or emerging materials, is widely studied to resolve the aforementioned issues of MOSFETs miniaturization. Some two-dimensional (2D) materials exhibit good potential; however, their practical applications in ICs require much time. The III-V semiconductors have killer applications; however, they are limited in special fields such as high voltages and large currents. That is, Si maintains its supremacy in ICs and this trend will continue for several years or even several decades.
Gate-all-around (GAA, also known as a surrounding gate) MOSFET [1][2][3][4][5][6][7][8][9][10] allows the highest control over electrostatic properties in all MOSFET structures and thus exhibits the strongest immunity to the short-channel effect. GAA MOSFETs are expected to replace Fin FETs as the primary device in Si ICs over the next few decades, as indicated by the International Roadmap for Devices and Systems (IRDS). This trend is important for CMOS logic circuits. The reason is that: MOSFET-based memories may be replaced by emerging non-volatile memories such as spintronic-based magnetic random-access-memory [11][12][13]; however, CMOS logic circuits have no competitors presently. Companies (such as TSMC and Samsung) have announced the application of lateral GAA (LGAA) MOSFETs in their CMOS logic circuits from the 3-nm technology node; however, LGAA has no superiority in integration as compared to other structures.
Three-dimensional (3D) architectures are widely studied to increase the integration of ICs. Currently, 3D stacking of chips or wafers [14][15][16][17] has been successfully applied in some products. However, the device distance between stacked chips or wafers is rarely less than 10 µm, which is too long, considering the electrical resistance and transfer delay, especially for logic circuits. Complementary FETs (CFETs, developed by companies such as IMEC and Intel) that stack different MOSFETs in the vertical direction (PMOS on NMOS, or NMOS on PMOS) could enhance CMOS integration [18][19][20][21][22] and presently become widely used for logic circuits. However, a compatible process for the heterostructures (PMOS and NMOS) is required. Furthermore, it is difficult to stack more than two MOSFET layers for CFETs, which is also because of process limitations.
Vertical GAA (VGAA), first reported at the IEDM conference in 1988 by Toshiba [1], were widely studied owing to their possible easy integration in the vertical direction. However, conventional VGAA MOSFETs face an asymmetric source/drain issue owing to the fabrication process [1][2][3][4][5][23][24][25][26][27][28][29][30][31][32], which prevents their practical applications. In early 2021, the authors first developed a process for the fabrication of the symmetric-source/drain vertical GAA MOSFET (referred to as ultimate VGAA, UVGAA); a novel 3D IC architecture with stacking UVGAA-based devices (CMOS and/or SRAM) in the vertical direction was also developed [33,34]. In December 2021, IBM and Samsung announced that a vertical transport nanosheet technology could be used for "beyond LGAA" owing to its superior electrical properties [35]. This vertical transport nanosheet technology is intrinsically a VGAA structure; therefore, it suffers the asymmetric source/drain issue as conventional VGAA MOSFETs and a comprehensive method has been used to improve device symmetry [35]. The aforementioned studies, one from academia [33] and the other from the industry [35], are expected to rekindle the interest in VGAA MOSFETs.

Fabrication process of SLGAA MOSFETs
SLGAA MOSFETs are formed by inserting an oxide insulator layer between stacked channel layers of conventional multi-channel LGAA MOSFETs [36][37][38][39][40][41][42][43][44][45][46][47][48][49]. Several special fabrication steps, not contained in the fabrication process of vertically stacked multi-channel LGAA-MOSFETs, are developed for SLGAA MOSFETs below. Figure 1(a) shows a traditional process of LGAA MOSFETs [36][37][38][39][40][41][42][43][44][45][46][47][48][49], which includes the epitaxial growth of SiGe/Si/SiGe multi-layers. Si in the multi-layers is used as the channel, whereas SiGe functions as a buffer layer for epitaxial growth of Si and a sacrificial layer for Si protection during the process. In this study, SiO 2 is deposited to sandwich the SiGe/Si/SiGe epitaxial layers, which is used to protect the epitaxial layers during the process. Figure 1 (b) shows the top image of the aforementioned multi-layers. A Si 3 N 4 hard mask was deposited to protect the entire structure as shown in Fig. 1 (c). Subsequently, a pattern was fabricated as shown in Fig. 1(d) using lithography and etching technology; here the middle part is the channel and the two sides are the source and drain. Because vertical layers are used for different SLGAA MOSFETs in this study, the multi-channel for one SLGAA MOSFET could be realized in one layer (not in vertically stacked layers as in the conventional case) using the pattern in Fig. 1(e). The mono-channel is discussed as shown in Fig. 1(d) for illustration. A SiGe layer is formed to fill the removing region of Fig. 1 (d) and the composite is then changed to Fig. 1 (f). Si 3 N 4 is then removed ( Fig. 1 (g)). Finally, SiO 2 is removed, followed by a polishing process, which causes only the SiGe left on the top of the device as shown in Fig. 1 (h). The Si channel is now wrapped with SiGe.
Following the process discussed in Fig. 1 (h), a SiO 2 layer is deposited. This SiO 2 becomes the insertion layer to separate the vertically stacked LGAA MOSFETs as previously introduced. The top view is shown in Fig. 2 (a); the three longitudinal cross sections along x 0 -x 0 ', x 1 -x 1 ', and y 0 -y 0 ' directions are discussed below. The cross-section along the x 0 -x 0 ' direction is shown in Fig. 2 (b), which is the entire channel image and has no change as compared to the initial composite shown in Fig. 1 (a). The cross-section along the x 1 -x 1 ' direction is shown in Fig. 2 (c), Si could be found on the two sides, which results from pattern formation in Fig. 1 (d). The cross-section along the y 0 -y 0 ' direction is shown in Fig. 2 (d). Here, the square Si channel is designed by optimization of the Si channel thickness in Fig. 1 (a) and pattern formation in Fig. 1 (d). The channel could also be designed as a rectangle shape for a nanosheet channel and the multi-channel could equally be designed and realized.
The aforementioned process is a simplified typical fabrication process of single-layer LGAA MOSFET; the process could be repeated for vertical stacking. The longitudinal cross-section of a double-layer stacking structure is shown in Fig. 3 (a). Notably, the two layers are separated by the sandwiched SiO 2 layer. A Si 3 N 4 hard mask is then deposited to protect the channel region as shown in Fig. 3 (b). Subsequently, SiGe is removed from the two sides ( Fig. 3 (c)) and poly-Si (p-Si) is deposited (Fig. 3 (d)). Here, the concave shape results from the isotropic etching of SiGe. After the aforementioned steps, the Si channel is wrapped by SiGe, whereas the two sides (source and drain regions) are only Si (p-Si and epitaxial Si).
The Si 3 N 4 hard mask at the channel region used in Fig. 3 was then removed and another Si 3 N 4 hard mask was deposited to protect the source and drain (the top view is shown in Fig. 4 (a)); subsequently, SiGe was etched around the Si channel. SiGe and the concave part of p-Si could be removed by dry etching. After the aforementioned steps, the longitudinal cross-section along the x 0 -x 0 ', x 1 -x 1 ', and y 0 -y 0 ' directions of the composite are shown in Figs. 4 (b), 4 (c), and 4 (d), respectively.
Thermal oxidation is then used for the following purposes: (1) Modification of the channel surface (interface between the semiconductor and oxide, refer to the channel interface oxide in Fig. 5(a)) to enhance the properties of MOSFET, which is because thermal oxidation can effectively modify the shape, surface, and variability of Si nanopillars or nanowires [50][51][52][53][54][55].
(2) Formation of the spacer between the gate and source/ drain (spacers oxide in Fig. 5), which is because the oxidation at the sidewall of a Si nanopillar or nanowire has a lower oxidation speed (owing to self-limiting oxidation) compared to oxidation of the Si bulk [53,54]. Thus, the spacer oxide is much thicker rather than the channel interface oxide, as shown in Fig. 5 (a). Therefore, the spacer oxide could be partly left after the removal of the SiO 2 in the channel interface (Figs. 5 After the deposition of the high-k gate oxide and gate, a longitudinal cross-section of the composite along the × 0-× 0' and y0-y0' directions are shown in Figs. 6 (a) and 6 (b), respectively. The gate at different layers may contact each other, this can be resolved by etching the sidewall of the composite. Finally, the p-Si at the two sides is removed (Fig. 6 (c)) and the source/drain electrode are deposited (Fig. 6 (c)) to form the basic structure of SLGAA MOSFETs. In addition, the source/drain electrode at different layers may contact each other, which could be also resolved by etching the sidewall of the composite. The fabrication of the contact line, followed by the formation of stairs to separate SLGAA MOSFETs at different layers, is a well-developed semiconductor process similar to that of the 3D NAND flash memory [56][57][58], could refer our previous work [33].

Three-dimensional logic devices of SLGAA MOSFETs
As previously introduced, the GAA MOSFET is expected to replace the Fin FET as a primary device in CMOS logic circuits over the next few decades, according to IRDS. In this section, the application of SLGAA in CMOS logic circuits is discussed. A typical CMOS circuit is shown in Fig. 7 (a), whereas a typical structure of three stacked CMOSs based on SLGAA MOSFETs is shown in Fig. 7 (b). Notably, the inserted oxide insulator layers between different MOS-FET layers are neglected for easier illustration. In an actual fabrication process, the gate oxide and gate materials should be optimized for PMOS and NMOS, which is not discussed here. The sequence of fabrication of three stacked PMOS (or NMOS) and the fabrication of the contact line is flexible and further stacking is possible in a real condition. Obviously, high integration CMOS could be achieved.
A CMOS NAND logic circuit is shown in Fig. 8 (a), whereas a schematic of the design sample of a CMOS NAND logic circuit is shown in Fig. 8 (b). Here, the inserted oxide insulator layers between different MOSFET layers are neglected for easier illustration. Similar to the stacked CMOS shown in Fig. 7 (b), the design for NAND logic circuits is also flexible (i.e., all four MOSFETs of the NAND logic gate in one layer) and further stacking could also be expected. Notably, the design and optimization are also available for other CMOS logic circuits. For example, A CMOS NOR logic gate can be realized by changing the position of PMOS and NMOS (V dd and V ss should be simultaneously changed) in Fig. 8 (b). Therefore, high integration of CMOS logic circuits can be realized by SLGAA MOSFETs.

Discussions
MOSFET miniaturization has been guided by Moore's law for more than 50 years and has been of significant benefit to Si ICs; however, this will be obsolete owing to the limitations of physics and processing. Although the "beyond CMOS," "More Moore," and "More than Moore" are widely studied, Si-based MOSFETs are still the primary devices in ICs and this trend will continue for a while. The shortchannel effect and the difficulty in further size shrinkage are two main difficulties faced by Si ICs, especially for logic ICs. The short-channel effect of miniaturized MOSFETs could be decreased by the GAA structure. In the absence of significant innovation for semiconductor processing, further size shrinkage is difficult and 3D stacking becomes the only solution for high integration. This is the motivation of this research (for LGAA MOSFET) and its sister article (for VGAA MOSFET) published in 2021 [33]. The use of the existing technology or equipment for innovation is the basis for the modern semiconductor industry. Currently, LGAAs are widely used in both industry and academia [36][37][38][39][40][41][42][43][44][45][46][47][48][49].
Therefore, SLGAA is proposed in this study. Because semiconductor manufacturing is complex for a single organizer, we share our considerations before the release of our experimental results, which aims to attract more researchers to contribute to the IC industry and thus modern civilization. Based on the aforementioned considerations, three main questions are discussed below.

Feasibility of SLGAA MOSFETs
A key question for this study is whether the SLGAA MOSFETs could be fabricated or not. The answer is yes, for the following reasons: the process developed in this study is based on the vertically stacked channel for one LGAA MOSFET; the only difference is that an insulator is inserted between channels. In case the proposed method is not considered, an extreme method could be used for the fabrication of SLGAA MOSFETs, which follows the fabrication process of the vertically stacked channel for one LGAA MOSFET, but inserts an oxide layer between channels. After the fabrication of the separated channels, the    Fig. 1; other method to solve this issue is to form a thin poly-Si buffer layer on SiO 2 before SiGe deposition, and this poly-Si buffer could be oxidized in the steps shown in Fig. 5 and then removed. Therefore, SLGAA MOSFETs could be fabricated using the existing semiconductor manufacturing conditions. In addition, SLGAA MOSFETs are being fabricated in the authors' lab and the experimental details and results compared with UVGAA MOSFETs will be released soon.
Other questions need to be answered. The first question is on the formation of the spacer by thermal oxidation. The authors are experienced in controlling the oxidation of nanosized Si [50][51][52][53][54][55]; based on previous results, modification of the channel surface (shape, surface, and variance of Si) and the formation of a spacer between the gate and source/ drain, could be precisely controlled through self-limiting oxidation of a nano-sized Si. The second question is on ion implantation. Junction-less structure [59], which can avoid the doping concentration gradient near junctions for sub-10-nm GAA-MOSFETs, is well established. In this study, ion implantation was performed during the epitaxial growth of Si. The third question is on the formation of stairs to separate SLGAA MOSFETs at different layers. This is a well-developed semiconductor process similar to that of the 3D NAND flash memory [56][57][58].
In addition, thermal noise may be an issue for the stacking structures including UVGAA, SLGAA, and CFETs. The tuning of the distance between stacking devices, the usage of low resistance materials, and the development of novel technology (structure and materials) for thermal dissipation, should be considered to address this common issue for not only the 3D structures but also all ICs based on miniaturized MOSFETs.
Above all, the implementation of SLGAA MOSFETs is feasible.

Advantages of SLGAA MOSFETs
Compared to the vertically stacked multi-channel LGAA MOSFET, performance enhancement and variability reduction of SLGAA MOSFETs could be expected for the following reasons: In almost all reports on vertically stacked multi-channel LGAA MOSFETs, the channels stacked in the vertical directions have different shapes (cross-section perpendicular to the current direction of the channel are different), which is because depth etching usually has a tapered shape for current semiconductor processing. However, the gate and drain voltages are the same for these vertically stacked channels and the channel current is size (or diameter)-dependent. Therefore, the current in stacked channels for conventional multi-channel LGAA MOSFETs is in different environments, resulting in uncontrollable electrical characteristics (i.e., the sub-threshold swing and the threshold voltage). However, for multi-channel SLGAA MOSFETs, the multi channels are in the same layer ( Fig. 1(e)), thus the electrical parameters can be controlled. Therefore, SLGAA MOSFETs could be associated with higher performance and reduced variability. Notably, the several layers of SLGAA MOS-FETs in the vertical direction are fabricated layer-bylayer; therefore, the tapered shape of depth etching of current semiconductor processing could be avoided, resulting in good uniformity. The simultaneous fabrication of gate , the gray lateral wire, for PMOS; blue lateral wire, for NMOS; green part, for gate oxide; red part, for the gate; pink wire, contact wire; yellow wire, the contact wire oxide, gate, and source/drain for SLGAA MOSFETs stacked in the vertical direction also improves uniformity. Notably, the aforementioned uniformity problem is the main setback for current ICs and intensifies with MOS-FET shrinkage.
High integration is another advantage for SLGAA MOS-FET. To date, only the UVGAA MOSFET developed by the authors have a high integration potential [33]. The other MOSFET structures could not be stacked for multi-layers as that of SLGAA and UVGAA structures. UVGAA seems to have the highest integration potential because its process originates from terabit cell array transistor 3D NAND flash memory [56][57][58], which could stack over 100 layers presently. Further, the VGAA MOSFET is considered "beyond LGAA" from the electrical properties obtained by IBM and Samsung [35]. However, using the existing technology for innovation is the basic method in the modern semiconductor industry. SLGAA MOSFETs originate from LGAA MOS-FETs (which are widely studied now); they are therefore promising for use in practical applications earlier, as compared to that of UVGAA MOSFET structure. Furthermore, the SLGAA structure is likely to be used for future applications of 2D materials because its channel is from thin films, whereas the UVGAA structure is difficult to be applied to 2D materials. In addition, both SLGAA and UVGAA MOS-FETs could develop into III-V semiconductors [60][61][62][63][64][65][66][67][68].
Because the six-transistor SRAM cell contains two CMOSs and two NMOSs, high-integration 3D SRAM with a flexible design, similar to CMOS logic ICs as previously discussed, could also be designed through SLGAA MOS-FETs and its process is developed in this study.
Notably, the combination of SLGAA-MOSFET-based CMOS logic devices and the SLGAA-MOSFET-based SRAM to form 3D hybrid circuits is expected to be used for the computing-in-memory. The 3D architecture with high integration potential makes the developed SLGAA MOS-FET an attractive field for next-generation ICs.

An open question for GAA MOSFETs
Owing to its high electrostatic controllability, the GAA structure is developed to decrease the short-channel effect caused by MOSFET miniaturization. A circular channel (cross-section) should be most immune to the shortchannel effect. Interestingly, traditional GAA MOSFETs (especially those developed by industry researchers) have nanosheet (normally ellipse cross-section) channels [36][37][38][39][40][41][42][43][44][45][46][47][48][49]. As explained, nanosheets have larger widths, and thus larger currents compared to nanowires. However, a multi-nanowire channel could have a larger width than that of a nanosheet in the same footprint. This has not been reported. That is, in the same footprint, a multi-nanowire channel could have a larger channel current than that of a nanosheet when the channel width is the only parameter considered. Furthermore, a circular Si (nanowire) could exhibit better interface modification and reduced variability through oxidation as compared to other Si nanostructures [50][51][52][53][54][55]. Therefore, the reason why Si nanosheets are widely used in LGAA MOSFETs should be attributed to that, Si nanosheets have better strengths compared to Si nanowires which prevents channel deterioration during the fabrication process. As it is well-known, LGAA with a suspended channel in some steps of the fabrication process is easy to deteriorate [33].
An open question is whether the current theoretical models for nanowire/nanopillar-based GAA MOSFETs built on experimental data, without considering the channel deterioration, are precise or not? Because the depletion layer of GAA MOSFET channels depends on the diameter of the Si nanowire (or nanopillar) [2,3], which makes the question more difficult. For a small Si nanowire (or nanopillar), full depletion may occur. In this case, the entire nanowire/ nanopillar may work as a channel to transfer current, thus a large current could be expected. An optimized process and meticulous engineering are necessary to understand the intrinsic physics of current in GAA channels, including novel quantum characteristics. The process developed in this study is promising to contribute the open question because it has advantages such as controllable electrical characteristics and reduced variability, as introduced above.

Conclusions
A fabrication process for SLGAA MOSFETs, which stacks LGAA MOSFETs in the vertical direction, is proposed for the first time. Furthermore, high-integration 3D logic ICs (such as stacked CMOS in the vertical direction and CMOS NAND logic circuits) were developed. Finally, the feasibility and advantages of SLGAA MOSFETs, as well as an open question on GAA MOSFETs, were discussed. These novel 3D architectures with stacking devices in the vertical direction laid the foundation for next-generation ICs.