Thermo-optic phase shifters based on silicon-on-insulator platform: state-of-the-art and a review

Silicon photonic platforms offer relevance to large markets in many applications, such as optical phased arrays, photonic neural networks, programmable photonic integrated circuits, and quantum computation devices. As one of the basic tuning devices, the thermo-optic phase shifter (TOPS) plays an important role in all these applications. A TOPS with the merits of easy fabrication, low power consumption, small thermal time constant, low insertion loss, small footprint, and low crosstalk, is needed to improve the performance and lower the cost of the above applications. To meet these demands, various TOPS have been proposed and experimentally demonstrated on different foundry platforms In this paper, we review the state-of-the-art of TOPS, including metal heater, doped silicon, silicide, with silicon substrate undercut for heat insulation, folded waveguide structure, and multi-pass waveguide structure. We further compare these TOPSs and propose the directions of the future developments on TOPS. Graphical abstract


Introduction
Benefiting from the complementary metal-oxide-semiconductor (CMOS) compatibility, silicon photonics is becoming a key technology for implementing high-density photonic integrated circuits (PICs) with complex functionalities [1][2][3]. The functions of these PICs are usually achieved through phase shifters [4,5]. Tuning principles of phase shifters are mainly based on the thermo-optic effect, the electro-optic effect, or the nano-opto-electro-mechanical effect [6][7][8]. Some other types of phase shifters have also been proposed and used extensively [9,10]. The thermo-optic coefficient of silicon in the C band over the temperature range 300-600 K can be written as [11] Therefore, the refractive index of a waveguide can be changed through a thermo-optic phase shifter (TOPS). The values of thermo-optic coefficient and heat conductivity are about 1.8 × 10 −4 K -1 and 149 W/mK, respectively [12]. Compared with the TOPS, electro-optic phase shifters always have a greater modulation bandwidth due to the free-carrier plasma dispersion effect. However, these devices usually suffer from substantial insertion loss due to freecarrier absorption [13]. Although the phase shifter based on the nano-opto-electro-mechanical effect has low power consumption, it is hard to fabricate. In addition, this type of phase shifter is liable to break down due to mechanical fatigue [14].
As a result of simple design, easy fabrication, low cost, and small footprint, the TOPS is widely used for photonic devices and large-scale integrated PICs on the silicon-oninsulator (SOI) platform [15][16][17]. Typical photonic devices that use the TOPS are Mach-Zehnder interferometer (MZI) [18][19][20], micro-disk [21], and micro-ring resonator (MRR) [22][23][24]. The TOPS in these photonic devices is used to change the phase of light by locally controlling the temperature in the phase-shifting region with TOPS. However, it is worth mentioning that the modulation bandwidth of TOPS is less than one hundred of kilohertz, the TOPS is only suitable for applications that do not require high modulation speed [25][26][27][28]. Regarding these characteristics of TOPS, monolithic integrated PIC with TOPS have been applied in some special applications, such as optical neural networks dn dT = 9.45 × 10 −5 + 3.47 × 10 −7 × T − 1.49 × 10 −10 × T 2 K −1 .
[ [29][30][31], quantum photonic devices [32][33][34], optical phased array [35,36], reconfigurable optical add-drop multiplexers (ROADMs) [37], programmable photonic circuit [38][39][40], and thermally-tunable optical delay lines [41]. The requirements of these PICs for TOPS will be discussed in Sect. 4. Many researchers are working toward improving the performance of TOPS [42][43][44][45]. Methods including air-gap trench or silicon substrate undercut post-processing, folded waveguide, and multi-pass waveguide have been proposed and demonstrated. A trade-off between the power consumption and the thermal time constant has also been investigated [46,47]. In this paper, we give an overview of the current status of the TOPS based on silicon photonics technologies. More specifically, we focus on the TOPS that is ready for massive application and fabricated in foundry platforms, including IMEC, AMF, IBM, OpSIS, CUMEC, and so on, by a standard silicon fabrication process, We also discuss the outlook for further development of TOPS, at the end of this paper.

Principle of TOPS
A TOPS is composed of a waveguide structure and a resistive heater. As shown in Fig. 1a and c, the shape of a waveguide on the SOI platform can be a strip or rib structure. Typically, both of them consist of a 2.0 μm silica lower cladding, 220 nm silicon core, and 2.0 μm silica upper cladding. Figure 1a-h provides the cross-sections of different kinds of TOPS, which will be discussed in detail in Sect. 3.
Due to the wide variety of materials and design complexities offered by CMOS technologies, the material used for the resistive heater can be doped silicon, silicide, or metal wiring. The line resistivity and fabrication process of the three types of heaters are different, which makes it possible to design heaters with different dimensions.
Generally, the amount of phase shift caused by resistive heater can be expressed as [48] where λ is the wavelength of the light, dn eff ∕dT is the thermo-optic coefficient of the silicon waveguide, L is the length of TOPS, and ΔT denotes the change of temperature. Since ΔT is caused by the action of the resistive heater, it can be written as Here, η is the utilization tuning efficiency of drive power, P is the power consumed by the resistive heater, C p is the heat capacity of the waveguide, ρ is the material density of the waveguide, and S is the cross-sectional area of the waveguide. The amount of phase shift can be written as The tuning efficiency of TOPS is usually expressed in terms of electrical power needed for a π phase shift (P π ), which can be expressed as Therefore, the tuning efficiency of TOPS is mainly determined by the utilization tuning efficiency of drive power. An effective way to improve the tuning efficiency of TOPS is reducing heat leakage to the environment.
In addition to tuning efficiency, the thermal time constant is also an important factor for TOPS. The thermal thermal time constant of TOPS can be written as where H is the heat capacity of the heated waveguide, and G denotes the thermal conductance of the waveguide to the environment. H and G can be expressed as Here, A is the area of heat flow. By substituting Eqs. (2) and (6) into Eq. (5), the thermal time constant can be rewritten as Therefore, the thermal time constant is influenced by the utilization efficiency, the area perpendicular to the direction of heat flow, and the cross-sectional area of the waveguide. Moreover, the product of thermal time constant and power consumption, i.e., the figure of merit (FOM), can be expressed as which can be reduced by decreasing the area perpendicular to the direction of heat flow, such as by directly integrating a doped silicon heater with a waveguide. However, the insertion loss of this kind of TOPS is relatively large, which is not suitable for large-scale networks. In addition, the TOPSs with folded and multi-pass waveguide have been proposed to reduce power consumption. Adversely, this type of structure would increase the size of the footprint and insertion loss. The pros and cons of all these TOPS devices will be described in the next section.

Comparison of different TOPS
Many studies have focused on improving the characteristics of TOPS, such as by increased tuning efficiency, faster thermal time constant, lower insertion loss, and smaller footprint. According to the difference between the structural differences of these TOPSs they can be classified as a basic structure, silicon substrate undercut, folded waveguide, multi-pass waveguide, and integrated with diode.

TOPS with a basic structure
For a basic TOPS structure, a resistive heater of doped silicon or silicide is placed on both sides of a waveguide. At the same time, a metal resistive heater can be fabricated above the waveguide, as shown in Fig. 2. It needs to be mentioned that the resistivity of the heater line should be much larger than that of connecting wire, which is usually made of metal aluminum (Al) or copper (Cu). Almost all silicon foundry platforms can manufacture these types of TOPSs, whose performances are shown in Table 1. The columns include heater type, waveguide type, test structure, tuning efficiency, heating time, cooling time, and foundry.
The tuning efficiency of all these TOPS with a basic structure is about 20 mW/π. The minor differences among tuning efficiency and thermal time constant of these TOPS might be caused by the material characteristics, processing technology, and testing equipment. The characteristics of these TOPS fabricated on CUMEC and other foundries are on the same level. Moreover, the drive voltage of TOPS can be written as [16] Here, P is the drive power of TOPS, and R denotes the resistance of the heater in TOPS. To use CMOS compatible drive voltage, which is always less than 1.0 V, a heater of silicide elements is electrically connected in parallel utilizing Cu connections (see Fig. 3). The resistance can be small enough, using the parallel connection, to apply a low drive voltage [16]. As a result, this kind of TOPS operates with the tuning efficiency of P π = 20 mW/π and a thermal time constant of τ < 2.8 μs, using a 1 V drive voltage. Unfortunately, the excess optical loss is about 25 dB/cm, which is caused by scattering and absorption loss [16]. PR.
In addition, a TOPS based on a strip waveguide with a directly integrated doped silicon heater has been demonstrated by Watts et al. [48], as shown in Fig. 4. Although the thermal time constant is the same as the TOPS with an electrically parallel heater, the tuning efficiency is only 12.7 mW/π due to the silicon waveguide core itself being used as a resistive heater. The insertion loss of the TOPS with a directly integrated doped silicon heater is about 0.5 dB, which is not beneficial for a large-scale PIC.
Due to the fact that insertion loss of a TOPS with a directly doped silicon heater in Ref. [48] is high, a novel TOPS with low-loss has been proposed and experimentally proved by Harris et al. [51]. As shown in Fig. 5b, there is only an 800 nm wide channel connecting the contact region to the ridge waveguide, which efficiently restricts the outward propagation of heat. There is sufficient clearance between the guiding region and the p++-doped region of 2.44 μm to avoide insertion loss due to the free-carrier absorption. A 61.6 μm long TOPS is fabricated with a propagation loss of (0.23 ± 0.13) dB for 21 devices. At the same time, the P π of the device is (24.77 ± 0.43) mW/π and the thermal time constant of the device is 2.69 μs, which is similar to the results of TOPS in Refs. [16,48].
Furthermore, we proposed a hybrid TOPS and fabricated it on the CUMEC silicon foundry platform, as shown in Fig. 6a. Figure 6b is the curve of output power versus the drive power when the TOPS is placed on one arm of the MZI structure. Figure 6c shows the fitting line of the variation of phase shift versus the drive power. The slope of the fitting line denotes the tuning efficiency, which is about 18.61 mW/π. As shown in Fig. 6d, the thermal time constant of TOPS with a hybrid structure is much smaller than the TOPS with a basic structure, without sacrificing tuning efficiency.

TOPS with the silicon substrate undercut
The thermal conductivity of air, at 0.31 W/(m·K), is almost three orders of magnitude smaller than that of silicon, 150 W/(m·K). An air-gap trench and silicon substrate undercut post-processing have been chosen to reduce the heat leakage to the environment, as shown in Fig. 7. Table 2 is the experimental results for TOPS devices with silicon substrate undercut which have been designed and fabricated by different organizations. As compared to the TOPS with the basic structure, a significant improvement of tuning efficiency is achieved. However, the thermal time constant is adversely affected due to the reduced heat conductivity by the air-gap trench and silicon substrate undercut. When a TOPS with silicon substrate undercut is applied in one phase arm of the MZI structure the thermal time constant is no less than 266 μs [50,[52][53][54]. The relationship between thermal time constant and − 3 dB bandwidth (f −3 dB ) [55,56] can be written as Therefore, the − 3 dB bandwidth of TOPS with air-gap trench and silicon substrate undercut is below 2.6 kHz, which makes them unattractive for several emerging applications. Except for the structure in Ref. [54], all the other structures shown in Table 2 are fabricated on the SOI platform. After a standard back-end process, an air-gap trench was fabricated by deep-etching down to the silicon substrate.
Then, anisotropic selective silicon etching was applied to the silicon substrate to undercut the waveguides [52]. Perspective and cross-section images are shown in Fig. 8. Here, two 4.0 μm wide arm trenches are fabricated on both  To further improve the tuning efficiency of the TOPS, a folded waveguide and suspended structure have been adopted simultaneously [53], as shown in Fig. 10a. The two types of structures are used to increase the optical interaction length of the light with the heated region and improve thermal isolation, respectively. Finally, the tuning efficiency can be improved to 0.05 mW/π, which is an order of magnitude higher than the TOPS with silicon substrate undercut reported in other literature [50,54,57,58]. Here, a Michelson interferometer (MI) has been adopted to replace the MZI [57]. The measurement results have been shown in Fig. 10b, the measured power required to switch from the maximum to minimum transmission is only 50 μW, and the thermal time constant is 1.28 ms, including a rise time of 780 μs and fall time of 500 μs.
The process of producing silicon substrate undercut is much more complex than that of producing the basic structure, and this kind of TOPS on our silicon platform is still under development. At the same time, the temperature variation of waveguides versus different structures has been analyzed. As shown in Fig. 11, the temperature variation of the waveguide of TOPS with silicon substrate undercut is much larger than the TOPS with only an air-gap trench and basic structure, which means the tuning efficiency of TOPS with undercut is much higher than the TOPS with only an air-gap trench.
Although the tuning efficiency of TOPS can be improved by creating a vertical air-gap trench and silicon substrate undercut surrounding the silicon waveguide [50, 52-54, 57, 58], some drawbacks have also been caused. First, densely placed air-gap trenches or silicon substrate undercut structures over a large area limits the scalability of integration. Second, the reliability has been reduced due to the accumulated mechanical fatigue from temperature stress. Third, the thermal time constant has increased by about 20 times. Therefore, the TOPS with air-gap trench and silicon substrate undercut is unbeneficial for applications that require fast response, such as optical neural networks, quantum computation devices [15].

TOPS with a folded waveguide
Due to the fact that the area of heat flow is much larger than the cross-section area of the waveguide, TOPS devices with folded waveguides have been proposed and fabricated [57][58][59]. Recently, Chung et al. have reported an experimental demonstration of geometrical design optimization for improving the tuning efficiency of a low-loss silicon thermo-optic waveguide phase shifter on a standard silicon photonics platform (see Fig. 12) [59], whose footprint is only 0.0023 mm 2 . The TOPS has been experimentally measured using an on-chip MZI, and the results are shown in Fig. 13. The TOPS consumes 2.56 mW for a π phase shift over 100 nm optical bandwidth while achieving 1.23 dB optical loss. Besides, the − 3 dB bandwidth of the TOPS is about 10.1 kHz. Therefore, the P π ·τ product of the TOPS is about 88.57 mW/π·μs. In addition, a TOPS based on a densely distributed silicon spiral waveguide on an SOI platform has been experimentally demonstrated by Qiu et al. [60] (see Fig. 14). The phase shifter shows a well-balanced performance in all aspects. The electric power consumption is as low as 3 mW to achieve a phase shift, the optical insertion loss is 0.9 dB, the footprint is 67 × 28 μm 2 under a standard silicon photonics fabrication process without silicon air-gap trench or substrate undercut process, and the modulation bandwidth is measured to be 39 kHz, as shown in Fig. 15.
The FOM of the TOPS is about 33 mW/π·μs, which is a benefit for large-scale silicon PICs as an efficient fundamental unit. Compared with the TOPS with silicon substrate undercut, this kind of structure is much easier to fabricate with a lower FOM value. Besides, the tuning efficiency of this kind of TOPS can be adjusted by changing the folded times of the waveguide. Unfortunately, the insertion loss is positively related to the folded times of the waveguide. To obtain the optimal folded times of waveguide, we have fabricated TOPS devices with folded waveguide on the CUMEC silicon platform and have analyzed their performances in terms of a new figure of merit (FOM 2 ), accounting for the influence of the insertion loss: where IL is the insertion loss of the device. As shown in Fig. 16, the widths of the two adjacent waveguides are 450 and 500 nm. The two waveguides are interval distribution (11) FOM 2 = P π ⋅ ⋅ IL,   [60] in Fig. 17c, when the folded time of the waveguide is 2, the FOM 2 is smallest. Consideration of the actual layout, a TOPS composed of a threefolded waveguide is a benefit for a large-scale PIC. Figure 17a and b is the curve of the tuning efficiency and thermal time constant versus the number of folds of the waveguide.

TOPS with a multi-pass waveguide
As is well known, there is always a trade-off between the tuning efficiency and thermal time constant of TOPS. To improve the tuning efficiency of TOPS without sacrificing the thermal time constant, light recycling based on resonators has been employed to improve the utilization tuning efficiency of drive power. As shown in Fig. 18, a multipass TOPS that lowers power consumption to 1.7 mW per π phase shift has been experimentally demonstrated [43]. The heater is placed on the top of the waveguide. An tuning efficiency of 15.4, 4.6, 2.6, and 1.7 mW/π are measured in the 1-pass, 3-pass, 5-pass, and 7-pass phase shifter, respectively. This corresponds to a power-tuning efficiency enhancement of 3.3, 5.9, and 8.9 times in the 3-pass, 5-pass, and 7-pass phase shifter, respectively. Note that the factor of enhancement is slightly higher than the number of passes. This is because the effective refractive indices of the higherorder modes are more sensitive to temperature change due to stronger dispersion. A thermal time constant of 6.5 μs is measured, which is independent of the number of passes, as shown in Fig. 19.
The disadvantage of this kind of structure is its large footprint and insertion loss. To solve this problem, we propose a new structure, as shown in Fig. 21a. An antisymmetric grating has been adopted to achieve mode conversation between TE 0 mode and TE 1 mode, which has a smaller size and lower insertion loss [61]. Unfortunately, the grating used to implement high-order mode conversation is complex. Therefore, the TOPS with only mode conversation of TE 0 and TE 1 based on antisymmetric grating has been fabricated on the CUMEC silicon platform. Compared with the TOPS of mode conversation via the asymmetric directional coupler, the footprint of this kind of TOPS is smaller. Moreover, P π is closer to one-third of that of the TOPS with one pass waveguide. Significantly, the mode conversion only happens between TE 1 mode and TE 0 mode, which can reduce the insertion loss effectively.

TOPS with the integrated diode
When the complexity of the large-scale photonic circuit increases, the circuit needs to be driven by means of hundreds or thousands of contact pads and voltage sources. The contact pads always occupy a large space in the photonic chip. Besides, a great number of wires are needed to connect the active devices to the pads. Therefore, the interfacing with electronics for controlling and read-out becomes a limiting factor for the scalability of the system. In recent years, Wim Bogaerts proposed a novel structure of TOPS with an integrated diode [62], as shown in Fig. 22. As mentioned earlier, doped silicon can be used as a resistor material to implement a TOPS on the SOI platform. Instead of either P-type or N-type dopants to increase the conductivity of the heater, the main body of the heater can use N-type dopants, and the region near one of the electrical contacts can be doped by P-type, creating a PN junction inside the heater. This approach converts the standard heater to a diode in series with a high resistivity strip. The total length of the heater is 50 μm, where 8 μm is used for the P-type doped region. The width of the heater is 1.2 μm. The heaters are placed closed to the target waveguide, keeping a gap of 0.75 μm between the heater and the waveguide. The gap was chosen to be close enough to increase the power consumption of the heater yet avoid leaking of the light from the waveguide to the heater. The heater and the waveguide have different widths to minimize coupling due to phase matching. The tuning efficiency of the TOPS is about 15-20 mW/π. Furthermore, a diode-based TOPS in a matrix topology, grouping the heaters in sets of M columns and N rows, has been proposed and experimentally demonstrated, as shown in Fig. 23. In this arrangement, the anodes of the diodeheaters are connected in the same row together, while the cathodes are connected in the same column together. Here, the rows and columns of the matrix are defined as control lines and driving channels. It is possible to address one specific phase shifter in the matrix by setting the voltage level at its correspondent control line at a low level (GND) while setting the voltage of its correspondent driving channel at a high level (V+).
Moreover, the matrix circuit can be divided into five identical sub-circuits along a single column, each containing one driving channel and three control lines, as shown in Fig. 24a. This requires a total of eight contact pads (and pulse width modulation (PWM) driving sources) to drive all 15 phase shifters needed to operate the circuit simultaneously. Figure 24b shows the time traces of a single driving channel in a circuit with N = 3 control lines.
In addition, time multiplexing has been adopted to improve the flexibility of this method. 1/N, where N is number of control lines, of the total cycle can be used by a TOPS at the same time. Therefore, the number of bond pads and power sources of a matrix arrangement that enables the driving of N × M phase shifters are (N + M) by using the PWM signal to implement multiplexed control. This technique is especially useful in silicon PICs with many TOPS devices but without enough space for electrical connections.

Discussion
As described above, there are many kinds of TOPS devices that use the SOI platform. Each kind of TOPS has advantages and disadvantages. To allow researchers to better choose the type of TOPS according to their demands, the performances of some typical TOPS are listed in Table 3. It is worth noting that the TOPS designed by the fabless organizations is not represented in Table 3.  Fig. 23 a 1 × 16 splitter tree circuit consisting of 15 tunable couplers, each of which is a balanced MZI with a TOPS in one arm. b Electrical connectivity of the 15 phase shifters. They contain a diode in series and are connected to three control lines and five driver channels [62] As shown in Table 3, a heater in the TOPS is generally made of metal, doped silicon, or silicide on the SOI platform. For a TOPS with a basic structure, the tuning efficiency is about 20 mW/π. When the PIC consists of more than 1000 TOPS of this configuration, the power consumption would be more than 20 W. To reduce power consumption, further improvements should be made to improve the tuning efficiency of TOPS devices. Silicon substrate undercut is an effective way to improve the tuning efficiency of TOPS devices since the heat generated by the heater is mainly accumulated in the vicinity of the waveguide and does not leak to the environment. The tuning efficiency can be improved to about 1.50 mW/π, which is less than a tenth of that of a TOPS without silicon undercut. However, the thermal time constant of this structure is about 200 μs, which is unbeneficial for large-scale PICs. The requirement for TOPS devices for large-scale PICs, such as optical neural networks and optical phased arrays, are high tuning efficiency and fast switching time, i.e., small FOM. Moreover, a TOPS with a folded waveguide and multi-pass waveguide has been experimentally investigated to meet these needs. Unfortunately, the two kinds of TOPS would cause a higher insertion loss, which greatly limits the scale of an optical neural network or optical phased array. It is worth mentioning that the TOPS of a hybrid structure can improve the thermal time constant without sacrificing tuning efficiency and increasing insertion loss. This kind of TOPS has not been widely used in PIC since the improvement is not obvious. Besides, the thermal crosstalk effect can strongly affect the application of TOPS on PIC. To solve this problem, many approaches have been adopted, such as optimizing the chip layout, isolating thermal diffusion, developing temperature-insensitive devices, and packaging with a thermo-electric cooler (TEC).
Note that, high phase tuning efficiency is the requirement for all applications for TOPS devices. When the TOPS is used for adjusting the working point of the photonic device, such as the Mach-Zehnder modulator, fast switching time is not necessary. However, when the TOPS is used in reconfigurable silicon photonic circuits, such as optical neural networks, optical-path-routing switches, optical phased arrays, quantum processors, and programmable photonic circuits, high tuning efficiency and fast switching time are required at the same time. Furthermore, the scale of these circuits is closely related to the loss and footprint of TOPS. In summary, the TOPS with high phase tuning efficiency, fast switching time, low loss, and small footprint, is very promising for various applications on the SOI platform.

Conclusion
This work provides an overview of various TOPS devices on the SOI platform, together with a brief theoretical explanation and a review of the TOPS devices fabricated on different silicon foundry platforms. Compared with other foundries, the CUMEC silicon platform can provide both design and fabrication of all these TOPS   [62]. a A single driving channel ChX connecting three MZIs to control lines. b Control mechanism of the sub-circuit devices at the same time. Low loss, small thermal time constant, higher phase tuning efficiency, and addressable TOPS devices are requirements for achieving further development.