A novel lambda negative-resistance transistor in the 0.5 μm standard CMOS process

A novel negative-resistance transistor (NRT) with a Lambda shaped I–V characteristic is demonstrated in the 0.5 μm standard CMOS process. To save on the number of component devices, this device does not use standard device models provided by CMOS processes, but changes a MOSFET and a BJT into a single device by fabricating them in the same n-well, with a p-type base layer as the MOSFET’s substrate. The NRT has a low valley current of −6.82 nA and a very high peak-to-valley current ratio of 3591. The peak current of the device is −24.49 μA which is low enough to reduce the power consumption of the deivce, and the average value of its negative resistance is about 32 kΩ. Unlike most negative-resistance devices which have been fabricated on compound semiconductor substrates in recent years, this novel NRT is based on a silicon substrate, compatible with mainstream CMOS technology. Our NRT dramatically reduces the number of devices, minimizing the area of the chip, has a low power consumption and thus a further reduction in cost.

Negative-resistance transistors (NRTs) have been researched for nearly 100 years, and are types of devices with negative resistance characteristic, which means the slope of their I-V curve is negative in certain regions. NRTs have a vast potential in many types of digital logic gates and memory circuits [1][2][3], such as the high-density static RAM made by Wu et al. in 1983 [4], the D flip-flop by Cheng and Duane in 2006 [5], the static RAM by Chen et al. in 2009 [1] and the spin-torque-transfer (STT) magnetoresistive RAM made by Halupka et al. in 2010 [6], etc. More recently, there have been many other negative-resistance devices such as carbon nanotube negative-resistance devices [7], metal-insulatormetal diodes on insulating films [8,9], and the resonant tunneling diode which have attracted much attention and been demonstrated in III-V compound semiconductor substrates. However, these devices are not all compatible with standard CMOS technology [10]. A demonstration based on CMOS technology would widen the application scope of the NRTs, but also reduce the processing difficulties and increase their manufacture rate. Therefore, a suitable Si-based negative-resistance device compatible with the CMOS process has become more and more interesting to circuit designers.
In this paper, a novel voltage-controlled NRT is presented. This device is designed and fabricated by using of the standard 0.5 m CMOS process, mainly applied to digital logic circuits such as logic gates and RAMs. As is well known, the typical CMOS logic circuit is constructed by a number of MOS or BJT devices [11,12], for example a D flip-flop on CMOS technology is constructed using nearly 20 MOSFETs. One BJT and two resonant tunneling diodes could also form a D flip-flop, but could only be realized in a compound process. Under these conditions the novel NRT is the best choice because it needs only two NRT devices to displace the 20 devices and still be compatible with CMOS technology, dramatically reducing the number of devices and the area occupied. This characteristic is particularly evident when used in large-scale logic arrays [13]. The working current of the device is several tens of microamperes, which is quite low compared to most negative resistance devices. There are types of negative resistance devices that work under several milliamperes or more, such as silicon controlled rectifiers and voltage controlled oscillators. However, the device mentioned here is mainly used in digital logic circuits, where the smaller working currents result in lower power consumption, which is one of the most important parameters of the digital logic circuits.
The equivalent circuit of an NRT is shown in Figure 1(a) which employs an n-channel depletion MOSFET and a lateral pnp transistor [14]. There are three terminals in the NRT named the Base (B), Collector (C) and Emitter (E) terminals as shown in Figure 1(a). The source and substrate of the MOSFET are connected internally, working as the base terminal of the NRT. The drain of the MOSFET and base of the BJT are connected externally by metallization. The gate of the MOSFET and collector of the BJT are also connected externally by metallization, working as the collector terminal of the NRT. The emitter of the BJT still works as the emitter of the NRT and is grounded.
Both the base-emitter voltage (V BE ) and collector-emitter voltage (V CE ) of the NRT are fixed, with a negative bias voltage. The resistor R c is used to modify the impedance of the device in the positive-resistance region. Figure 1(b) shows the basic structure of the NRT. Different from the common MOSFET and BJT structure of the standard CMOS process, the MOSFET is fabricated into the p-base layer which is typically the base region of an npn bipolar transistor. The p-base layer is also a p-type semiconductor material working as the substrate of the MOSFET. In this way the lateral pnp transistor and the MOSFET can both be fabricated into the same n-well, minimizing the total area of the NRT. Figure 2 shows the microphotograph of the NRT. The left part is the n-channel depletion MOSFET and the right part is the lateral pnp-BJT. To minimize the area occupied by the chip, the width to length ratio of the MOSFET gate is 20 m/2 m, the base area of the lateral pnp transistor is 11.2 m 2 , the emitter and collector area of the lateral pnp transistor are both 15.4 m 2 , and the total size of the device is 21 m × 23 m.
The typical I CE /V CE characteristic of the NRT is shown in Figure 3(a) which was measured using a Keithley 4200 instrument at room temperature. As analyzed previously, the input base voltage V BE and collector voltage V CE are both fixed with a negative bias. The V CE is from 0 to 1 V, with a 0.02 V per step, while the V BE is from 0 to 2.5 V, with a 0.1 V per step.
It is well known that the negative resistance R N equals the derivative of V CE with respect to I C , i.e. R N =dV CE /dI C . R N is positive when the curve of the I C /V CE is upward, and it is negative when the curve is downward. However, the value of R N will not remain the same. The changes in R N depend on the changes in the slope of the curve. For example, in Figure 3(a), when V BE is 2.5 V, the curve of I C /V CE is marked by two dotted ellipses, which represent the Negative-Resistance Region I and Region II respectively. The peak value of I CE can be observed when V CE is around 180 mV. The average value of R N is the ratio of the difference between the peak and valley value of V CE divided by the difference between the peak and valley value of I CE [15]. When V BE is 2.5 V, the average value of R N is about 32 k. The figure shows that in Region I, the slope of the curve decreases as V CE increases. Therefore the negative resistance decreases as V CE increases; in Region II, the slope of the curve increases as V CE increases. Therefore the negative  resistance increases as V CE increases. The relationship of R N /V CE is shown in Figure 3(b). The variation tendencies of R N in the Negative-Resistance Region I and II confirm the preceding analysis about the slope. The value of V CE in the Negative-Resistance Region I and II is between 150 and 240 mV. The value of R N drops dramatically when V BE is higher than 240 mV.
The peak-to-valley current ratio is the ratio of the peak value of the current (I P ) divided by the valley value of the current (I V ) [15]. For example when V BE is 2.5 V, I P is 24.49 A and when V CE is 180 mV, I V is 6.82 nA when V CE is 1 V. Therefore the PVCR is about 3591, and high enough for most digital logic circuits such as inverters and D flip-flops. The valley current is also an important parameter, which represents the value of the leakage current when the device is off. A 6.82 nA valley current is small enough for low power consumption.
In conclusion, we have designed and fabricated a novel lambda NRT in the 0.5 m standard CMOS process. The equivalent circuit of the NRT is constructed using an n-channel depletion MOSFET and a lateral pnp-BJT. Both the devices are reconstructed into a single n-well and have the p-base layer as the substrate of the MOSFET, dramatically reducing the number of devices and the area occupied on the chip. The NRT successfully achieved the negative resistance characteristic with a very low valley current of 6.8217 nA and low power consumption. After analysis and calculation, the average value of R N is about 32 kΩ with a V BE of 2.5 V. The NRT has a relatively high PVCR of 3591 and is compatible with standard CMOS technology. It has huge potential value in digital logic circuits and RAM applications.