Hardware Implementation of a Fixed-Point Decoder for Low-Density Lattice Codes

This paper describes a field-programmable gate array (FPGA) implementation of a fixed-point low-density lattice code (LDLC) decoder where the Gaussian mixture messages that are exchanged during the iterative decoding process are approximated to a single Gaussian. A detailed quantization study is first performed to find the minimum number of bits required for the fixed-point decoder to attain a frame error rate (FER) performance similar to floating-point. Then efficient numerical methods are devised to approximate the required non-linear functions. Finally, the paper presents a comparison of the performance of the different decoder architectures as well as a detailed analysis of the resource requirements and throughput trade-offs of the primary design blocks for the different architectures. A novel pipelined LDLC decoder architecture is proposed where resource re-utilization along with pipelining allows for a parallelism equivalent to 50 variable nodes on the target FPGA device. The pipelined architecture attains a throughput of 10.5 Msymbols/sec at a distance of 5 dB from capacity which is a 1.8\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document}× improvement in throughput compared to an implementation with 20 parallel variable nodes without pipelining. This implementation also achieves 24\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document}× improvement in throughput over a baseline serial decoder.


Introduction
Low-density lattice codes (LDLCs) are a special class of lattice codes proposed by Sommer et al. [1], whose construction and intended applications are substantially different from that of more familiar error-correcting codes such as low-density parity check (LDPC) codes, Polar, and Turbo codes. Lattice codes in general have shown great theoretical promise to exploit interference, possibly leading to significantly higher rates between users in multi-user networks.
Research on LDLCs has concentrated on demonstrating the theoretically achievable performance limits of LDLCs, and until now there has been no reported hardware implementation, mainly due to the complexity of message-passing for LDLC decoding.
In this paper we investigate a field-programmable gate array implementation (FPGA) of a fixed-point decoder for low-density lattice codes. LDLCs are lattice codes whose construction was shown to allow for iterative decoding via message passing.
While linear error-correcting codes, e.g., LDPC and Polar codes, are based on finite fields, lattice codes are their Euclidean-space analog. In binary linear error-correcting codes, bit sequences are encoded into binary codewords before modulation, and the modulo-2 sum of any two binary codewords is again a binary codeword. In contrast, a lattice code directly outputs a point (i.e., lattice point) in Euclidean space, and the real-vector sum of two lattice points is again a lattice point, i.e., lattice codes have algebraic structure. Lattice codes have been shown to be effective for applications such as mitigating multi-user channel interference using the compute and-forward framework, and dirty-paper coding, by exploiting a code structure that is not present in error correcting codes [2][3][4][5][6][7][8].
LDLCs have a sparse (low-density) H matrix (inverse generator matrix) that renders iterative decoding (also called message-passing) an efficient decoding method for LDLCs [1,9]. Despite this, implementation of the algorithm presented in [1] is not practical, either in software or hardware. This is primarily due to the fact that when the channel is additive-white-Gaussian-noise (AWGN), the messages exchanged between check and variable nodes in the iterative decoding algorithm are continuous functions, i.e., Gaussian mixtures. This is in contrast to many decoding algorithms for error-control codes, e.g., LDPC decoders, where messages can readily be reduced to single numbers such as loglikelihood ratios.
In prior work on LDLCs [1,[10][11][12][13], the continuous functions are either sampled and quantized or represented as Gaussian mixture messages denoted by parametric lists. In [1], each message is quantized to 1024 samples, which provides good accuracy in decoding but results in large storage and computational load. In [10,12,13], the messages are represented by Gaussian parametric lists of means, variances and coefficients. Nevertheless, as the decoding iterations progress, the number of components in the Gaussian mixtures grows exponentially and the implementation eventually has extremely large storage requirements and computational cost. To limit the number of components in the mixtures, Gaussian reduction algorithms are used to reduce the size of the messages after each decoding iteration. These methods reduce the message size significantly; however, even with all these reduction techniques, LDLC decoding is costly.
The emphasis of the literature to date in [1,[9][10][11][12][13][14][15][16][17] is on demonstrating theoretically achievable performance limits of LDLCs; not much work has been done towards a hardware implementation of LDLC decoding. Our work contributes in this direction with the aim to achieve a hardware implementation of a decoder for LDLCs. Several approximations are required to make this decoder feasible in hardware. However, these could result in a loss of performance.
In this work, the messages exchanged in iterative decoding are reduced to a single Gaussian using a momentmatching method in each decoding iteration [14]. Thus, only the mean and variance of a single Gaussian is exchanged between a check node and a variable node at each iteration. Since integer computations are inherently simpler than floating-point operations, a fixed-point arithmetic implementation is preferred. An important aspect of a fixed-point implementation is to determine the minimum number of bits for the required range and precision. A detailed quantization study is presented to find this minimum word length for fixed-point arithmetic. Efficient numerical techniques are then applied to approximate the required non-linear functions (division and exponentiation).
Previously we reported a serial LDLC decoder in FPGA, and in order to exploit the parallelism of iterative decoding, several parallel message computation blocks were included in the decoder [18]. Here we present a novel pipelined approach to implement the single-Gaussian LDLC decoder. With this design we achieve more than ∼ 24× improvement in throughput over the two-node serial implementation.
The outline of this paper is as follows. Section 2 defines lattice codes and LDLCs, and describes the properties and constraints for the LDLC H matrix. In Section 3, the iterative decoding algorithm is presented for a single-Gaussian decoder. Section 4 presents the implementation details of the single-Gaussian LDLC decoder in fixed-point arithmetic. Specifically 4.2 provides details of the quantization study and simulation results, followed by 4.3, which provides the key aspects of the decoder architecture, FPGA hardware implementation and results. Conclusions are provided in Section 5.

Basic Definitions
Below, we provide a definition of LDLCs and some performance limits.
Definition 1 An n-dimensional lattice, Λ ⊂ ℝ n , is defined as all the integer linear combinations of n given linearly independent basis vectors, g 1 , … , g n ∈ ℝ n . Taking the basis vectors as the columns of the generator matrix G, (i.e. G = (g 1 , … , g n )) the lattice Λ is given by Definition 2 A low-density lattice code is an n-dimensional lattice code defined by a non-singular generator matrix that satisfies the condition that the constraint matrix, H = G −1 , is sparse.
Following [1], the H matrix is chosen to be a regular Latin-square matrix, i.e., a matrix where every row and column has the same degree, d, of non-zero values h 1 ,h 2 , … ,h d except for possible sign flips and change of order. The sorted sequence of values h 1 ≥h 2 ≥ … ≥h d > 0 is termed as the generating sequence.
In [19], Poltyrev suggested a generic definition of capacity for lattice codes with no power restriction. According to this, capacity for lattice codes is defined as the maximal possible codeword density that can be recovered reliably at the receiver. This generalized capacity implied that there exists a lattice G of high enough dimension n that enables transmission with arbitrarily small error probability, if and only if the channel noise variance, where e = 2.71828... is Euler's number (also known as the natural constant).
Thus the maximal performance limit for the lattice codes can be given by 2 = n √ � det(G)� 2 ∕2 e. Since for the designed LDLCs, | det(G)| = 1 , the theoretical noise (performance) limit is 2 = 1∕2 e . For an AWGN channel without power restrictions, it is possible to quantify distance from capacity as the distance of the noise variance 2 from 1∕2 e . To compute this, we first take the ratio of 2 and 1∕2 e , i.e., 2 ∕(1∕2 e) and then convert the ratio to decibels (dB). All decoder frame error rate (FER) performance curves in this paper are thus measured with respect to the distance from capacity, −10 log 10 (2 e 2 ) (dB).
For this work, an H matrix of degree 3 is generated with the sequence {1, 1

LDLC Iterative Decoding Algorithm
The sparse nature of the bipartite graph corresponding to the H matrix makes iterative message passing the preferred method for decoding LDLCs [1]. The AWGN channel model for LDLCs is given as where x is the transmitted lattice codeword (i.e., x = Gb ) , y is the received noisy message and z is a vector of independent and identically distributed (i.i.d.) Gaussian noise samples with common variance 2 .
In the parametric LDLC decoders, lists of means, variances and coefficients corresponding to the Gaussian mixture messages are exchanged between check nodes and variable nodes during the iterative decoding process [10,12,14]. For the single-Gaussian LDLC decoder implemented in this work the mixture messages are reduced to a single-Gaussian and only the mean and variance are exchanged.
A Gaussian mixture, GM(t), with N components is defined by where m k , V k and c k are, respectively, the mean, the variance, and the mixing coefficient/weight of the k th component. A Gaussian mixture can then be efficiently represented by a set of triples {(m 1 ,V 1 , c 1 ), … , (m N , V N , c N )} . If the coefficients sum to 1, i.e., ∑ N k=1 c k = 1 , then the Gaussian mixture is normalized. A single Gaussian is a special case of a Gaussian mixture when N = 1 , and can therefore be represented by the triple (m, V, c). If the single Gaussian is normalized, i.e., c = 1 , then this can be reduced to the mean-variance tuple (m, V).
Some intermediate steps in the single-Gaussian LDLC decoder generate Gaussian mixtures; however these mixtures are reduced to a single normalized Gaussian before message passing. Thus only mean-variance pairs are exchanged as messages between check nodes and variable nodes.
The basic steps of the iterative decoding algorithm for a single-Gaussian decoder are summarized below.

Initialization
At the start of the decoding process, each variable node x k receives the single-Gaussian message from the AWGN channel given by (y k , 2 ) . Here y k is the mean and 2 is the variance of the single Gaussian. This initial message is sent along all the edges connected to this variable node.

Basic Iteration: Check Node Message
Each check node has d input messages coming along the edges connected to it with weights h p , p = 1, … , d as shown in Fig. 1a where h p is one of the h 's with a possible sign flip.
The incoming messages are single Gaussians given by (m , V ) , where = 1, 2 … , d . The mean of the outgoing check node message along the edge with weight h p is obtained by first multiplying for ≠ p , the mean of the th message with h h p , then summing the results over ≠ p and a sign flip.
The variance of the outgoing check node message along the edge with weight h p is obtained by first multiplying for ≠ p , the variance of the th message with , then summing the results over ≠ p . The outgoing message is therefore the single-Gaussian (m p , V p ) given by,

Basic Iteration: Variable Node Message
As shown in Fig. 1b, each variable node receives d single-Gaussian messages along its edges denoted by (m , V ) for = 1, 2 … , d.
There are two primary steps performed at the variable nodes, a 1) periodic extension step and a 2) product step.
1) The periodic extension step generates periodic Gaussian mixtures from the incoming messages. In [1], this step is performed as a part of check node operations and the variable node receives the periodically extended Gaussian mixtures. However, in the single Gaussian decoder, the messages received from the check nodes are single-Gaussian messages and the periodic extension step occurs at the variable nodes [14]. This significantly reduces the storage requirements for the check node messages. In the periodic extension step, the mean of the incoming check node message along an edge with weight h l is first periodically extended as below, where i denotes the i th extension. In principle, the variable i can take any integer value, but in practice the range is restricted so that the Gaussian components are near the channel message. This restriction is reasonable as the channel message is close to zero when evaluated far from its mean. 2) The outgoing variable node message along the edge with weight h p is computed by taking the product of the channel message, denoted by (m 0 , V 0 ) , and all the Gaussian mixtures, except the mixture associated on that edge. This is then further reduced to a single-Gaussian using the second moment-matching-method [20].The product of two Gaussian mixtures is calculated by the pairwise multiplication of each possible pair of components between the two mixtures. The product of two Gaussians is a scaled Gaussian. If two Gaussian components with triples (m 1 ,Ṽ 1 ,c 1 ) and (m 2 ,Ṽ 2 ,c 2 ) are multiplied, the resultant Gaussian is given by the triple (m F , V F , c F ) calculated as,

Final Decision
After every iteration, we estimate the decoded integer vector b . To get b , first an estimate ŵ k of the transmitted codeword element x k for k = 1, 2 … , n is computed. The variable, ŵ k is the mean of the single Gaussian obtained after the multiplication of the channel message and all the incoming check node messages (without omitting any) at each variable node (as described in Section 3.3) and the moment matching step [14]. Then b is estimated as where ⌊⌉ denotes coordinate-wise integer rounding [21]. The decoded integer vector, b , is computed after every decoding iteration and the iterative decoding process is terminated as soon as decoding is successful. Early stopping reduces the average number of iterations required for decoding and is commonly used in iterative decoding [17,[22][23][24][25].

LDLC Decoder Implementation
The product-step at the variable node generates a Gaussian mixture that must be reduced to a single Gaussian before it can be sent along an outgoing edge of the node. The single Gaussian approximation for the Gaussian mixture is computed using the second-moment-matching method, now described below.
For a Gaussian mixture message denoted by triples of mean, variance and mixing coefficients, i.e., by is obtained by first normalizing the mixture according to r k = c k ∕( ∑ N k=1 c k ) , and then parameters m and V are calculated as For improved numerical stability, at the variable nodes, the smallest allowable variance is limited to a certain minimum value denoted . In the literature a of 0.03 2 was adopted [12]; however, based on our simulations, can be increased to 0.1 2 without any loss in decoder performance, where is the standard deviation of the received Gaussian channel message. In this work, any variance less than 0.1 2 is increased back to 0.1 2 .
Moreover, all variances in this implementation are measured relative to the channel noise variance, e.g., for V = 2 in the implementation the actual variance is 2 2 .
Simulation results presented for a single-Gaussian decoder are for random lattice codewords in the integer range b ∈ L n , where L = {−2, −1, 0, 1, 2}.

Number of Decoding Iterations
In [1,11,12,14], the reported performance results for the LDLC decoder are for 200 decoding iterations. However, in order to obtain reasonable decoding latency as well as limit power consumption, fewer decoding iterations are preferred. Therefore finding a suitable number of decoding iterations is an important step towards a feasible hardware. Figure 2 shows the decoder performance versus number of decoding iterations at a distance from capacity of 3.5 dB as well as 5 dB. As the graph suggests, with 20 decoding iterations, the decoder can achieve comparable performance to 200 decoding iterations, but in significantly less run time.

Fixed-Point Quantization Study
In the design space of this work, a fixed-point arithmetic is sufficient to implement the decoder in hardware (demonstrated further in the section). However, a key aspect of fixed-point arithmetic is to determine the range and precision requirements of the design.
In fixed-point representation, every number has a fixed word length of W bits that consists of W i integer bits, W f fractional bits and a sign bit. In this paper fixed-point representations are denoted by Q W i .W f , e.g., Q10.8 indicates 10 bits to represent the integer range and 8 bits for the fractional precision, and one sign bit (19 bits total).

1) Approximation of non-linear functions:
The fixed-point implementation has two non-trivial non-linear functions: division and exponentiation.
a) Approximation of division function using Newton-Raphson method: A straightforward method to approximate division in fixed-point is integer long division. However, integer long division computation, i.e., (u, a) = (u ≪ W f )∕a can be expensive in terms of time and hardware. As an alternative, can also be implemented as where _ (a) is the reciprocal of a calculated using the Newton-Raphson (NR) method, which is then multiplied with u using the fixed-point multiplication function, . For the Newton-Raphson method, convergence to the correct solution depends critically on a reasonable initial guess. In a fixed-point decoder, this initial guess is obtained using a look-up table (LUT). To reduce the look-up table size and minimize approximation errors, we do not approximate the reciprocal of a, but instead, the fixed-point number a is written as q × (s ⋅ 2 P ) where P is an integer, q is ±1 and s is a non-negative fixed-point number with 1 ≤ s < 2 . The reciprocal of s is then calculated using _ . This reciprocal is multiplied with u, scaled back by 2 −P and further multiplied with q to get the value of u/a.
In this method, the reciprocal of s is always in the range 0.5 < 1∕s ≤ 1 , which can be represented precisely enough with a small number of fractional bits.
The division function is thus implemented in the fixed-point LDLC decoder as (See Fig. 3

),
Simulations were performed to find an optimal LUT size to get a reasonable initial guess for the NR approximation and ensure high accuracy of the division result with a minimum number of iterations. Specifically the performance with LUT sizes of 4, 8 and 16 entries were computed by numerical simulation using the procedure described below. For LUT sizes of 8 and 16 entries, similar FER performance is obtained after two NR iterations while one NR iteration results in performance loss compared to 2 iterations. For a LUT size of 4 entries, FER performance is 0.2 dB worse than that of the 8 entry LUT even after 2 or more iterations. Based on these (u, a) = q × ( (u, _ (s)) ≫ P). For a fixed-point number, s, we use the 3 bits after the leading 1 (since 1 ≤ s < 2 ) as the index for the LUT to obtain the initial guess. The complexity of this method is constant time, i.e., O(1) [26]. b) Approximation of exponential function using LUTs: A direct implementation of the exponential function in FPGA has large resource requirements and design complexity. However LUT-driven methods make an exponential implementation feasible in limited FPGA resources.
In an LDLC decoder implementation, the exponent is always non-positive. Specifically, we approximate exp(−a∕2) for a ≥ 0 , where the division by two accounts for the factor of 1 2 in the exponent of (8).
For ease of computation, the exponential function exp (−a∕2) is written as the product of three easily computable terms.
In particular, a is decomposed into 3 parts as where P 0 < P 1 < P 2 are the positions of the least significant bit of each part and I 0 , I 1 , I 2 are integers that depend on a such that 0 ≤ I 0 < 2 P 1 −P 0 , 0 ≤ I 1 < 2 P 2 −P 1 and 0 ≤ I 2 < 2 W i −P 2 . Figure 4 illustrates the relationship between a and I 0 , I 1 and I 2 .
Since I 0 is comprised of P 1 − P 0 bits, its range is from 0 to 2 (P 1 −P 0 ) − 1 . Likewise I 1 is comprised of P 2 − P 1 bits and its range is from 0 to 2 (P 2 −P 1 ) − 1 and I 2 comprises of W i − P 2 bits with its range from 0 to 2 (W i −P 2 ) − 1.
Then the exponential is given as, Decomposing a into three smaller parts thus allows for three smaller look-up tables instead of a single large lookup table to approximate the exponential.

2) Optimal word length and Newton-Raphson (NR) iterations for fixed-point decoder:
In order to find the optimal word length for the fixed-point representation, simulations are performed for different values of W i and W f . Figure 5 compares the frame error rates for different values of W f while keeping W i large and varying the number of NR iterations for block length n = 1000. Figure 6 compares decoder performance for different values of W i while W f is fixed.
A key observation in Fig. 5 is that at 4.5 dB the FER for Q14.8 with 2 NR iterations is 0.13 dB better compared to Q14.18.
The LDLC decoder is a sub-optimal decoder because it is both iterative and parametric in nature. Therefore, it is anticipated that some approximations could potentially improve the decoder performance.
To understand this behaviour, simulations were performed with a floating-point decoder where the components of the Gaussian mixture message at the variable node that have coefficients less than a certain threshold, denoted , are removed from the Gaussian mixture. As illustrated in Fig. 7, the FER does not monotonically increase with , but instead achieves a minimum at approximately ≈ 0.03 . Based on these simulation results, an appropriate choice of W f helps the decoder by naturally underflowing the fixed-point representation of small coefficients. However if W f is further reduced, then performance deteriorates.
A similar trend has previously been seen in published fixed-point Turbo decoders, where the quantization methodology leads to fixed-point implementations where the bit error rate (BER) can be slightly better than the BER of floating-point implementation [27].

Figure. 7
Effect of removing small coefficients from Gaussian mixture in floating point LDLC decoder at −10 log 10 2 e 2 = 4 dB, n = 1000 (reproduced from [18]). Figure 6 plots the effect of a different number of integer bits on the decoder performance. The results reported here demonstrate that the decoder performance degrades with smaller W i due to the computation errors that occur from the saturation in arithmetic operations, primarily multiplication.
Based on the results in Figs. 5 and 6, a word length of 21 with 12 integer bits, 8 fractional bits and a sign bit is an appropriate choice for a fixed-point representation. As seen in Fig. 6 the single-Gaussian, Q12.8 (with 2 NR iterations) achieves an FER of 3 ⋅ 10 −3 at a distance of 5 dB from capacity that is slightly better than the floatingpoint decoder.

LDLC Decoder FPGA Implementation
We now present our FPGA implementation results including 3 architectures: A) an architecture with a single check node and a single variable node, B) an architecture where parallelism and hardware resources are exploited to implement 20 variable nodes and a single check node and C) an architecture with a single check node and with two-stage pipelining to achieve an effective parallelism equivalent to 50 variable nodes.
Architecture A) A single check node and a single variable node: A fully parallel LDLC decoder implementation is large and does not fit on the target reconfigurable device. However, there are possible approaches to build the complete decoder on a target FPGA device that can fit a few check and variable nodes.
To better understand the issues involved in an LDLC decoder implementation and make key estimates, e.g., resource requirements and performance, as a baseline design In order to compute the outgoing messages from a check node, c k , the message routing network looks up the variable nodes connected to c k and the edge weights associated with these connections from the respective ROMs. Then, it fetches the corresponding means and variances from the variable node message memory and the check node message processing block computes the outgoing messages. The Figure. 8 Block diagram of a two-node serial single-Gaussian LDLC decoder with one check node and one variable node (reproduced from [18]).

Figure. 9
Block diagram for the mean computation of the outgoing messages at the check node. The mean is computed by first multiplying each incoming message with its respective edge weight (except the one on the outgoing edge), summing the results and further dividing the result of the summation by the outgoing edge weight along with a sign flip.
variable node message processing block receives the check node messages and computes the outgoing variable node messages in a similar fashion.
Check node message processing block The check node message processing block consists of check node unit that performs convolution of the incoming messages according to (3) and (4). Figures 9 and 10 show the mean and variance computations of the outgoing check node messages that can be implemented with only a few adaptive logic modules (ALMs), digital signal processing (DSP) blocks and registers. Figure 11 depicts the timing diagram for the check node message processing block in architectures A, B, and C.
Variable node message processing block The variable node message processing block consists of a variable node unit, . As discussed in Section 3.3, at each variable node unit, d − 1 periodically extended check node messages and the channel message are multiplied and the resulting product is reduced to a single-Gaussian using second moment-matching. To compute the variable node message efficiently, a forward-backward recursive algorithm is used [10].
The algorithm is initialized with the channel message. Let's denote the periodically extended messages with where = 1, 2 … , d and the Gaussian mixture reduction of Section 4 (including the normalization step) by .
The pseudo-code for this forward-backward recursion algorithm is given in Algorithm 1. Here " ⋅ " denotes product of Gaussian mixtures as described in Section 3.3.
Once the forward-backward messages, FW and BW for = 1, 2 … , d are computed, the outgoing variable node messages, i.e., (m , V ) for = 1, 2 … , d are obtained as, The estimate of the transmitted codeword, ŵ k is the mean of the computation, (FW 2 ⋅ BW 1 ). The top-level architecture of the variable node unit is presented in Fig. 12. The timing diagram for the variable node message processing block in architecture A is shown in Fig. 13.
The computation of FW j ⋅ j in Algorithm 1 computes the product of a single Gaussian ( FW j ) with a Gaussian mixture ( j ). The single Gaussian is normalized. Thus, it has a single component of weight '1'. The Gaussian mixture is obtained by periodically extending a normalized single Gaussian. Thus all the weights of the mixture are equal and are also '1'. In addition, all the variances of the mixture are equal to that of the single Gaussian that was periodically extended and hence, are all equal. Therefore, the term in (8), which must be computed for each component in the product FW j ⋅ j , is the same. Since the components in the product are explicitly normalized in the Gaussian mixture reduction step that follows the computation of the product, to reduce complexity, for the computation of the product FW j ⋅ j , the weights in (8)    Similarly, the weights in (8) are also replaced with (16) for the computation of the product BW (d−j+1) ⋅ (d−j+1) . This serial implementation was designed as a proof-ofconcept for LDLC decoding in hardware. However, more than one check node and/or variable node with design (16) optimizations can provide considerable improvement in decoding speed. Architecture B) A single check node and 20 variable nodes: The variable node unit described above requires 140 clock cycles for message computation while the check node takes a single cycle, and thus the variable node limits the throughput. Several parallel variable nodes can render variable-node message computation faster and boost decoder throughput significantly. To exploit the inherent parallelism of iterative decoding we implement 20 parallel variable nodes with the available resources on the target FPGA (of course, a larger FPGA could potentially fit even more variable nodes). Figure 14 shows the decoder architecture where the check node message processing block has a single check node and the variable node message processing block contains 20 parallel variable node units denoted by , with inputs { } and outputs, { } for p = 0, 1, 2 … , 19 . Figure 15 shows the timing diagram for the variable node message processing block in architecture B. The message routing network fetches check node messages for one variable node every clock cycle and the incoming messages are Figure. 12 High-level architecture of a variable node unit ( ) for d = 3 . At a variable node, x k , the incoming check node messages are periodically extended, FW and BW for = 1, 2 … , d are computed in computation block and finally the outgoing variable node messages, (m , V ) for = 1, 2 … , d and estimate for transmitted codeword, ŵ k ; is obtained in the computation block. Architecture C) A single check node and with two-stage pipelining to achieve an effective parallelism equivalent to 50 variable nodes: After additional data flow and design optimizations, in the variable node unit shown in Fig. 12, the computation block requires 109 clock cycles while the calculations in the computation block take 10 clock cycles. This implies that one computation block can be sufficient to process the output from 10 computation blocks (when pipelined), which could provide significant hardware savings.
For efficient variable node message computation, we implement a two-stage pipeline in the variable node message processing block. The first stage of the pipeline consists of 10 computation blocks that compute the FW and BW messages corresponding to 10 variable nodes, x k for k = 0, 1, 2 … , 9 , according to Algorithm 1. Further, the second stage block reads-in stage 1 output and computes outgoing variable node messages according to (15) corresponding to a variable node. The design components, primarily adders and multipliers, are reused in different clock cycles within the two pipeline stages. For convenience, this pipelined architecture is termed as . The resources on the target FPGA are sufficient to implement 5 parallel blocks ( for p = 0, 1, 2 … , 4 ), achieving a parallelism equivalent to 50 variable node units ( ), thus rendering significantly reduced computation time for each variable node message generation overall. Figure 16 shows the top-level block diagram of the variable node message processing block used in architecture C that consists of 5 blocks. Figure. 14 Top-level block diagram of the LDLC decoder with one check node and 20 parallel variable node units (reproduced from [18]).

Figure. 15
Timing diagram of the variable node message processing block in architecture B.
The sub-blocks of the pipelining inside the blocks are shown specifically for . Here, 10 forward-backward message computation blocks, i.e., { } with inputs, { } and outputs, { } for p = 0, 1, 2 … , 9 comprise the first stage of the pipeline. The second stage consists of the computation block with input, and output, . Figure 17 shows the timing diagram for the various signals used in the two pipelining stages of the block. The resource requirements and throughput of the variable node message processing block used in architectures A, B, and C, are provided in Tables 1 and 2 respectively. Based on Tables 1 and 2, it is evident that parallelism and pipelining boost throughput of the variable node message processing block significantly. However, it is achieved at extra hardware cost. Figure 18 shows a high-level block diagram for decoder architecture C, that consists of a single check node and 5 blocks.

Performance and Resource Usage
Decoder architectures A, B and C are implemented on an Intel FPGA (Arria 10, 10AX115N3F45I2SG) and the resource usage is provided in Table 3. All three architectures achieve the frame error rate shown in Fig. 6 at a clock frequency of 125 MHz. If the decoder is operated at a higher frequency, some critical paths in the design may have timing issues. Therefore, 125 MHz is the recommended fastest clock for our architectures in the target technology.

Figure. 16
High-level diagram of the variable node message processing block used in architecture C, that consists of 5 blocks. The two stage pipelining used in blocks is shown specifically for . Figure 19 shows the throughput comparison for these architectures. Architecture C attains a throughput of 10.5 Msymbols/sec at a distance of 5 dB from capacity which is a 24× improvement over the baseline implementation A and a 1.8× improvement over architecture B. Note that the decoder throughput varies over signal-to-noise-ratio (SNR) values due to early termination in the iterative decoding process.
To the best of our knowledge, there is no prior work on hardware implementation of LDLC decoders, and thus no direct comparator other than our previous paper [18]. Compared to [18], the work presented here achieves an overall improvement of 1.8× in decoding throughput over [18]. Figure. 17 Timing diagram of block used in variable node message processing block of architecture C. The waveforms are shown particularly for block.  The storage requirement for this implementation is O(n ⋅ d) and the computational complexity is O(n ⋅ d ⋅ R) where n is block length, d is degree for the LDLC design and R is number of the periodic extensions.

Conclusion
This paper has described the performance results and design strategies used for a fixed-point single-Gaussian LDLC decoder implementation in hardware. After developing approaches to address the complexities of the hardware implementation, e.g., efficient approximations of the nonlinear functions and a comprehensive quantization study, we have achieved a successful FPGA implementation of a decoder for low-density-lattice codes.
With the detailed knowledge gained from the serial and partially parallel single-Gaussian LDLC decoder implementations, this work can be extended to an LDLC decoder where messages exchanged are Gaussian mixtures. As an initial FPGA implementation of LDLC decoders, this work is key to future hardware implementations (FPGA or ASIC) of the LDLC decoders.
Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long Figure. 18 Top-level architecture for the LDLC decoder with a single check node and with two-stage pipelining to achieve an effective parallelism equivalent to 50 variable nodes.  Figure. 19 Throughput comparison of different decoder architectures for n = 1000 and clock frequency of 125 MHz (modified from [18]).
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