Analysis of energy consumption bounds in CMOS current-steering digital-to-analog converters

In this paper, an attempt to estimate energy consumption bounds versus signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) in CMOS current-steering digital-to-analog converters is presented. A theoretical analysis is derived, including the design corners for noise, speed and linearity for the mixed-signal domain. The study is validated by comparing the theoretical results with published measured data. As result it serves as a design reference to aim for minimum energy consumption. It is found that for an equivalent number of bits (ENOBs), the noise-bound grows at a rate of 22ENOB, whereas the speed-bound increases by 2ENOB−2 and is dependent on device dimensions. Therefore, as the technology scales down, the noise bound will dominate, which is observed for an estimated SNR of about 40 dB in 65 nm CMOS process. The linearity bound is derived from an analysis based on the assumption of limited output impedance, where it is found to be dependent on the device dimensions and increase at a rate of 2ENOB−1. The observations show that it is possible to achieve less energy consumption in all the design corners for different SNR and SFDR specifications within the Nyquist frequency, fs/2.

With communication standards such as 5G and mm-Wave communications, a DAC operating at higher channel bandwidths with maintained linearity is required, in turn, increasing the design challenges to maintain low-power consumption [7]. However, not much about the actual required power consumption in high-speed DACs has been reported [8]. Acquiring knowledge of the energy limitations required to achieve a certain SNR, SFDR, and signal bandwidth is relevant to identify how much power savings can be obtained. The analysis presented in this paper addresses power and energy consumption concerns from a design point of view.
A CMOS binary-weighted DAC architecture is utilized as the base model for our investigations. It is regarded to be the less power-hungry solution due to its intrinsic simplicity in the data conversion process. Moreover, the current-steering topology is considered as it is one of the preferred options for high-speed DAC operation since it has no need for buffers and provides a simplistic architecture.
A generic current-steering DAC is illustrated in Fig. 1 showing its main building blocks. Our study starts with a noise-limited analysis as the fundamental bounding condition. Then, speed and linearity requirements are added and addressed to determine how they could influence the energy required to meet the SNR and SFDR specifications. Fundamental building blocks, including switching drivers, buffers, and timing circuits are included in the model, but we have omitted the digital signal processing parts and other conditional circuitry as they are too diverse and application specific. We discuss the implications of this assumption.
The paper is organized as follows: In Sect. 2 a derivation of the SNR taking the noise contributions into account is presented along with the power consumption for a differential CS DAC. In Sect. 3 an elaborated analysis considering the power and energy consumption bounds for noise, speed, and linearity is presented. In Sect. 4 additional design considerations with respect to the bias network, output impedance and load resistance are discussed. In Sect. 5, data from reported measurement results are compared with the data obtained from the analysis which validates and motivates the theoretical results. Finally, the paper is concluded in Sect. 6.

Preliminary notes
In this paper, energy and power consumption bounds aimed at CMOS current-steering DACs are derived. We utilize a differential N-bit structure and a unary current I u representing the least significant-bit (LSB). Each single-ended output is terminated by a resistive load R L as shown in and the differential voltage swing at the output is.
The output swing is usually dictated and specified by the following blocks, like a power amplifier or mixer, dependent on the system architecture. Adjustments of the parameters I u , N, and R L , are then required to set the swing. Assuming a full-scale sinusoidal signal, the normalized output power delivered by the differential CS DAC in units of amperes 2 is Thermal noise will arise in both resistive loads, R L , and inside the DAC itself and will be present at the output which will in turn determine the SNR as well as the ENOB. We have selected to bound the thermal noise such that its power equals the quantization noise power. The total noise power then equals the sum of the thermal noise power, P Th , and the quantization noise power, P Q , which can be expressed in units of amperes 2 as The SNR is defined as the ratio between the signal and noise power and with (3) and (4) we get Fig. 1 Structural overview of a generic current-steering digital-toanalog converter (CS DAC) or expressed in dB as.

The analog domain
The power consumed by analog blocks in the selected Nbit current-steering DAC is where the supply voltage is V AVDD =V hr þ V swd =2, with V hr as the voltage headroom to bias the analog circuits. Figure 2 shows the switch current cell (CC) with the stacked transistors M sw and M cs as the switch and current source transistors, respectively. As will be explained in Sect. 3, a reduction of the current I u is limited by noise, speed and linearity requirements, whereas a reduction of V hr depends on the number of stacked transistors. The simplest differential current cell consists of two stacked transistors, offering the lowest headroom, V hr [9]. Transistor M cs operates as a current source, and its effective voltage, V eff ;M cs , is V gs;M cs À V th;M cs . To guarantee that the current source transistor M cs operates in saturation, the voltage V X in Fig. 2 should be V X ! V eff ;M cs . Transistor M sw operates as a switch, and when turned on, it is biased in saturation to achieve high output impedance [10]. The drain-to-source voltage, V ds;M sw , is set to aV eff ;M cs with a [ 0 and the voltage headroom can be written as.
For M sw to operate in saturation, its drain voltage, V d;M sw , needs to satisfy V d;M sw C V gt;M sw where V d;M sw = V hr , and V gt;M sw = V g;M sw À V th;M sw with V g;M sw as the voltage at the gate of M sw with respect to ground, and V th;M sw its threshold voltage, respectively. Substituting (8) into (7) and using V AVDD ¼ V hr þ V sw;d =2, the analog power consumption becomes To minimize this expression, it is clear that I u and V eff ;M cs should be minimized. In Sect. 3 we derive an expression to find the optimum V eff ;M cs for minimum P DACa due to noise constrains.

Digital domain
In the DAC model in Fig. 1, the digital blocks consist of switch drivers, timing circuits and clock/data buffers. Timing circuits are needed to synchronize data, but at a cost of higher power consumption and area. The digital blocks in our analysis are mainly implemented with CMOS static logic [11]- [13], but it is noted that current-mode logic (CML) is also utilized in high-speed DACs [14]. It is wellknown that digital power consumption equals [15] with P sw , P sc , P leak , and P sta as switching, short-circuit, leakage and static power. In the model, rail-to-rail voltage swing and no use of pseudo-CMOS logic cancels the static component P sta . Also considering ideal data/clock transitions reduce P sc to zero [16]. Albeit a potentially considerable factor in modern digital circuits, the leakage current P leak is omitted from our analysis. As a result, P sw remains in (10) and the P DACd for an N-bit CS DAC is.
where a 0!1 is the switching activity, i.e., the probability of a 0 ! 1 transition per clock cycle, C d is the capacitance contribution from the timing circuits/switching drivers and data buffers, V DVDD is the digital supply voltage and C clk originates from the clock buffers and due to that nature is scaled by a 0!1 =1.

Mixed-signal domain
Additional power dissipation comes from charging the gate capacitance, C g;sw , in the switch transistors (M sw1;2 in Fig. 2). The power consumption from the mixed-signal domain becomes [12,17] P DACm ¼ a 0!1 2 N À 1 À Á C g;sw V 2 g;M sw f s ð12Þ where C g;sw ¼ 2W sw L sw C ox =3 ? 2C g;ov , with C g;ov as the overlap capacitance, and V g;M sw the voltage swing at the gate of M sw1;2 .

DAC Power consumption
The total DAC power consumption, P DAC , is the sum of the power from the analog, digital and mixed-signal domains. In the worst-case scenario, when operating at the Nyquist rate with f sig ¼ f s =2 and a 0!1 = 0.5, P DAC can be approximated for N C 6 by.

Analog power bounds in CS DACs
We are now able to elaborate further on the expressions to find the optimum values that minimizes power consumption. Presented below is the analysis with respect to noise, speed, and linearity bounds.

Noise-limited bound
To obtain a noise-limited bound, uncorrelated thermal noise contribution from the current source transistors and the single-ended load resistors, R L , are taken into consideration. Flicker noise from the current source transistors is omitted due to its relevance only at low frequencies. The thermal noise from the gate resistance, R G , is neglected as it is small [18]. For a CS DAC operating with a signal bandwidth Df and a temperature T, the power of the thermal noise in amperes 2 is with k B and c as the Boltzmann and technology excess noise constant, and g m the transconductance of M cs given by Substituting (15) into (14), the thermal noise power is Since P Th is equal to the quantization noise power, it can also be expressed as Then (16) together with R L = V sw;d =2 2 N À 1 À Á I u yields with V as the ratio V sw;d =V eff ;Mcs Solving for I u in (18) with Df as the Nyquist bandwidth, f s =2 a lower bound for I u due to noise bounds is obtained and approximated for N C 6 Substituting (19) into (9) gives For minimum P DAC with respect to V eff ;M cs , we derivate (20) and set to zero: (21), we get an expression for V eff ;M cs that reaches a minimum P DACa;n as 4b Thus, V eff ;M cs is a function of V sw:d , b and c.
M cs , an expression that relates V eff ;M cs and V ds;M sw is found by expanding (22) as Solving for V eff ;M cs in (23), we get the following two roots Root r 1À is discarded as it is negative. Using the expressions for V ds;M sw and V sw;d , the effective gate voltage V eff ;M cs is calculated. The bound for P DAC due to the noiselimited condition is derived by substituting (22) into (20), where we get

Speed-limited bound
The speed of the DAC is limited by the response time of the complementary switching transistors, M sw1;2 , and the settling time of the output signal. The switching speed is related to the transit frequency, f T , which for submicron CMOS processes now reaches beyond 100 GHz [19]. The settling time is determined by the load's time constant R L C L , which also limits the output signal bandwidth to From (26), minimizing R L C L is necessary to achieve the highest bandwidth. R L is one of the design parameters, whereas C L is composed of all the capacitance present at the output node with respect to ground. Moreover, with C l as the drain-to-ground capacitance of the individual current cell as shown in Fig. 2.
Since M sw1;2 are operating in saturation, C l is reduced to the diffusion capacitance, and is determined by the device dimensions and technology parameters. Assuming that the bandwidth equals the Nyquist bandwidth, f s =2, and using (26), the sample frequency f s can be given in terms of C l by To maximize f s , this suggests utilizing the smallest C l given by the technology and minimum sized transistors should be used for M sw1;2 . The load resistance, R L can be reduced to increase f s , at the cost of augmented I u and P DAC to maintain a fixed V sw;d . Substituting for R L = V sw;d = 2 N À 1 À Á I u in (27) and solving for I u from the speed bound, we get.
For example, setting V sw;d = 1 V and C l * 0.1 fF, the currents I u;s and I u;n are normalized with respect to f s (GHz) and plotted versus the SNR in Fig. 3. A crossing point between I u;s =f s and I u;n =f s around an SNR of 45 dB is observed. For SNR \ 45 dB (N=8), the minimum I u , is dominated by the speed bound; and for SNR [ 45 dB, the noise bound dominates.
If the sizes of M sw1;2 are kept at a minimum for different magnitudes of current I u;s , adjustments in the voltage headroom V hr must take place to counteract the additional voltage drop. This effectively alters the V eff ;M cs and b. If instead V hr is chosen to be fixed, adjustments in the width of M sw1;2 , W sw , are necessary. For the latter, and as a firstorder approximation (without body-effect and channellength modulation), W sw , is sized according to where K ¼ l n C ox =2 and l n is the electron mobility and C ox is the gate-oxide capacitance per unit area. It is worth as the junction capacitance in F, l the junction length in m, and C jÀsw the sidewall capacitance in F/m. Consequently, C l becomes a function of I u;s , and therefore another expression for I u;s can be derived after substituting (28) into (29) as (30), in order to have mathematical consistency and maintain I u;s [ 0, the inequality 2KV eff ;M sw 2 [ pV sw;df L sw f s C 1 needs to be satisfied, which sets a bound for f s as From (31), the maximum f s is proportional to V eff ;M sw , and l n . On the contrary, a longer channel length L sw and C 1 reduces f s . Nevertheless, from (27), to achieve maximum BW, minimum C l is required, suggesting the utilization of minimum sized M sw1;2 . Then, P DAC due to speed-limited conditions is obtained by substituting (28) into (9), which yields

Linearity-limited bound
Sources of linearity degradation can be classified in terms of amplitude and timing errors [20,21]. Part of the amplitude errors is due to current mismatch in the output currents and threshold voltages in the M CS transistors is related to process and temperature variations as well as Fig. 3 Normalized I u over f s (sampling frequency) with respect to noise and speed bounds vs SNR with M sw1;2 drain-to-ground capacitance, C l , of 0.1 fF dimensions and the spacing, D, between MOS transistors as suggested by [22,23] with A b , A VT and S b as process-dependent parameters. To counteract for process variations, the transistors are increased in size and placed with reduced D. This does not imply power expense, but area utilization. Another source of amplitude error comes from limited output impedance, Z out j j, in the CC due to parasitic capacitances in the internal nodes. Hence, the output impedance reduces as the frequency of the signal reaches the Nyquist bandwidth. As an example, Fig. 2 shows the drain-to-ground parasitic capacitance in M cs , C x , at the common node V x , creating a pole which will be indicated in this section. Other CCs integrate more than one cascode transistor to augment the output impedance [24]. Initially, we limit ourselves to the single-stacked CC and no timing errors to treat the linearity-limited bound.
To analyze the linearity with respect to P DAC , the SFDR is taken for a differential DAC, which is expressed as [25,26] where x is the ratio between the AC amplitude, X AC , and the DC level, X DC , of the single-ended input signal. For a full-scaled signal we have X DC ¼ X AC ¼ 2 NÀ1 . Also, q0 G in (34) is given by with q G j j as the conductance ratio's magnitude, q G , as For a well-designed current source, q0 G is close to zero and (34) approximates Z out j j of the chosen current cell can be modeled as [27] Z out with x = 2pf sig , and R out the output resistance. As a firstorder approximation, R out for the single-stacked CC is R out % g m;sw r 0;sw r 0;cs ¼ 2 where g m;sw ¼ 2I u =V eff ;Msw , r 0;sw ¼ 1=k sw I u and r 0;cs ¼ 1=k cs I u , with k sw and k cs as the channel modulation values, and g m;sw the transconductance of M sw . The output impedance has a pole at 1=2pr 0;cs C x ¼ k cs I u =2pC x and the frequency response of Z out j j can be separated into the following regions f sig k cs I u =2pC x , and k cs I u =2pC x \f sig . These two cases are treated in more detail later in this section. Substituting for Z out j j in (36), and solving for Solving for q G j j in (28) for a full-scale input signal, and substituting for q0 with FðSFDRÞ = ffiffiffiffiffiffiffiffiffiffiffiffi SFDR 4 p =2 À 1. Substituting (41) into (40) for q G j j and solving for Z out j j gives Since R L = V sw;d = 2 N À 1 À Á I u , (42) can also be given by From (43) it is seen that a reduction in Z out j j is obtained either by reducing V sw;d or increasing I u at the cost of a higher power consumption. The unary current I u is obtained from (43) as and can be calculated from the SFDR and Z out j j requirements. The output impedance Z out j j is also a function of I u , see (39). Substituting (38) and (39) If f sig 1=2pr 0;cs C x , then (45) can be reduced to 4 ¼ Hk sw k cs V eff ;Msw À Á 2 , and the SFDR is obtained from the product k sw k cs V eff ;sw . This result does not depend on frequency nor I u . If f sig [ 1=2pr 0;cs C x , the term x 2 C s 2 dominates and I u can be expressed as The pole, 1=2pr 0;cs C x , equals k cs I u =2pC x , and is also a function of I u . A criteria to satisfy f sig [ 1=2pr 0;cs C x is defined when operating at f sig ¼ f s =2 as Substituting (46) into (47) yields If (48) is satisfied, the pole is located at a frequency below Nyquist, which can be expressed as k cs I u;l =2pC x \f s =2. The linearity-limited power bound when satisfying (47) and f sig ¼ f s =2 is found after substituting (49) into (9) as A similar analysis can be realized when adding a cascode transistor with M cs as illustrated in Fig. 4a The frequency response of Z out is shown in Fig. 4b [12], and it is divided in two regions separated by the zero gm cas =2pC cs .
Thus, for f sig [ gm cas =2pC cs , the pole becomes 1=2pr 0;cas C x , and V eff ;Mcs in (49) is substituted by V x instead.
The total power P DAC is calculated taking the noise, speed and linearity requirements into account. For the noise and speed bounds, the SNR is taken into consideration. For the linearity bound, the SFDR is instead used.

Power consumption design considerations
In addition to the analysis presented above, other aspects concerning power consumption are treated in this section, including the bias network, output impedance, and load resistance.

Bias network
The simplest bias network consists of a current mirror transistor connected at the gate of the current source transistors. However, long interconnections between the reference current mirror and the source transistors can lead to mismatch errors [28,29]. Hence, a more elaborated bias network can be used with added power consumption. The noise contribution from the bias network is modeled in Fig. 5. The noise power spectral density from the bias network corresponds to the current source I 2 n;bias . Also, the input-referred noise contribution of each current source i at its gate is model with a current source I 2 n;i . Then, the total noise, I 2 n;in , equals 2 N À 1 À Á I 2 n;i ?I 2 n;bias . I 2 n;in is coupled to the output node V x by the current source transistors. The noise from the bias network at the output is expressed in terms of the proportionality factor, g bias , with respect to the noise in the current source transistor. Thus, noise contribution can be expressed as As shown in appendix, g bias is inversely proportional to xC bias ð Þ 2 with C bias = 2 N À 1 À Á C g;cs þ C parasitics . Then, g bias approximates to zero for high-speed and resolution and omitted from the analysis.

Current source output impedance
From (45), when operating at f sig 1=2pr 0;cs C x , then k sw k cs V eff ;Msw H À Á 2 ¼ 4, which relates k Ã = k sw k cs with respect to the SFDR, V eff ;Msw and V sw;d , by In Fig. 6 with k ds and U 0 as technology parameters, L sw and L cs as the channel length of M sw and M cs . For reduced V hr , we have V DS;sw = V eff ;Msw and V DS;cs = V eff ;Mcs , simplifying (52) to To reduce k Ã , it is necessary to either increase L sw or L cs . Increasing L sw to reach higher output impedance, augments the mixed-signal power consumption as suggested by (12) and reduces the bound for f s according to (31). Consequently, L sw remains with minimum size in the analysis, and L cs is sized instead to satisfy (51), without extra expense in power consumption. Further on, L cs is sized based upon mismatch specifications in the current sources as suggested by (33). Therefore; L cs should be taken from the maximum L cs from these two analyses.

Output load resistance
Another important design consideration has to do with the selection of R L . Usually, an output resistance of 50 X is used to facilitate the matching of the output ports with other building blocks, e.g., reconstruction filters, RF baluns. If it is specified to achieve V sw;d = 1 V, I u can be found as From (54), it is shown that as N is larger, I u decreases for a fixed V sw;d and R L , which can compromise the SNR/ SFDR as explained in Sect. 3. Another approach is to choose I u from the SNR, or SFDR requirements, and calculate an optimum R L instead. A matching network can be used between the DAC output and external building blocks to have impedance matching and maximum power transfer.
As an example, Fig. 7 plots the load resistance R L versus SNR according to the noise analysis at different sample frequencies f s . The dash line corresponds to R L = 50 X, where we identify the crossing points with f s = 10, 1 and 0.1 GHz for SNR of about 60, 70, 80 dB. For SNRs where R L C 50 X from the noise bound curves, an R L = 50 X can be utilized instead as it does not compromise the SNR. Beyond the crossing points with higher SNR, the R L must instead be chosen from the noise bound. A similar analysis can be done for the speed and linearity bounds.

Verification with measurement results
To validate the theoretical analysis, the energy bounds, including analog, digital and mixed-signal power domains, for the three different design corners, i.e., noise, speed and linearity, are plotted in Figs. 8, 9 and 10 along with published measurement results. The publications use various types of current-steering DACs in different CMOS technologies. Table 1 lists the design and technology parameters utilized in the analysis. The capacitance values are obtained from a 65-nm CMOS process. Minimum sized switch transistors are used, and therefore, a range of allowed V ds;M sw voltages is specified. Table 2 lists the drain-to-source V ds;M sw values for 100 and 400 mV as well as the calculation of V eff ;Mcs /V x , b, V hr and V AVDD . Fullscale current and load resistance, I FS and R L , are determined by the unary current, I u , and consequently, are not listed in Table 1. The noise energy bounds are plotted for a temperature of 75°C. Figure 8 presents the energy consumption versus the SNR for the noise and speed design corners. The noise  Table 2. In Fig. 8, for SNR \ 50 dB, the two noise plots b 1 , b 2 and the speed bounds converge at energy levels above 0.1 pJ as the digital and mixed-signal energy consumption start to become more dominant. For SNR [ 50 dB, the noise bound dominates due to the strong exponential dependency of the ENOB according to (25). As SNR gets larger, noise plots b 1 and b 2 diverge, making it possible to see the implication of different switch voltages within the V ds;M sw range.
With respect to the ENOB, the speed design corner, the digital and mixed-signal components grow at a rate of 2 ENOB , whereas the analog grows at 2 ENOB-2 . The analog component is linearly dependent on C l , and scales down as device dimensions decrease. Thus, the speed bound is predominately dominated by the digital and mixed-signal components and grows proportional to 2 ENOB . In Fig. 8, we also see that the noise bound dominates. It grows at a rate of 2 2ENOB , and from SNR = 60 dB we see how this component dominates the exponential curve. Comparing measurement data in terms of noise bounds, it is observed that the data points follow the behavior of the curves b 1 , b 2 even for current-steering DACs implemented with currentmode logic (CML) [14,33,34], which suggests an agreement with the theory presented in Sect. 3.
Figs. 9 and 10 plot the linearity energy bound versus the SFDR for the b 2 case. Measurement data from 12-and 16bit DACs are presented. The linearity energy bound scales with device dimensions as it is a function of the commonnode capacitance, C x , and as a result, this bound is plotted for different CMOS process nodes. Some of the DACs utilize enhancement techniques to improve the SFDR at the cost of extra power consumption. The distortion reported in the measurement data come also from timing and amplitude errors, and not only limited due to output impedance. Therefore, the plots presented should be considered as a reference for comparison purposes between the linearity bound and the published measurement data.
In Fig. 9, the linearity bounds for a 12-bit DAC implemented in a 0.18 lm and a 65 nm CMOS processes are plotted along with measurement results from published 12-bit DACs in 0.18 lm and 65 nm CMOS processes to have a fair comparison between the theory and measured data. From Fig. 9, as is expected, we see that the measured results indicate a higher energy consumption with respect to the presented linearity energy bounds. It is observed a gap of about less than an order of magnitude in the data   [37] and [38], except for [39], which incorporates a delta-sigma-assisted pre-distortion scheme to compensate for current mismatch at the cost of increased power consumption. On the other hand, utilization of decoding logic in combination with randomization circuits in [37], and utilization of a thermometer decoder with delay equalizers along with master and slave latches in [38] elevate also the power dissipation. Figure 10 plots the energy consumption bound for a 65 nm CMOS processes, and 16-bit DACs manufactured in the same process node. The measured data report a higher energy consumption in comparison with the linearity energy bound, where it is observed how the measured data follows the bound trend as the requirement in the SFDR increases. Both [40] and [41] incorporate signal processing, in turn, increasing the overall power consumption as observed between the measured data and the linearity bound when operating with a channel bandwidth of f s =2.

Conclusions
A theoretical analysis was presented to derive the energy consumption bounds for the three design corners, including noise, speed, and linearity in CMOS current-steering DACs. From the study, the digital and mixed-signal power contributions for the different design corners are observed to be less significant as technology scales down because of smaller device dimensions and reduced parasitic capacitances. On the contrary, the analog energy bound for the noise corner does not scale with the device dimensions and dominates over the digital and mixed-signal power domains for SNR [ 50 dB. It is found that the analog energy bound is strongly dependent on the ENOB by 2 2ENOB , which agrees with the trend observed in the measured data when plotting energy consumption versus SNR.  In summary, the noise energy bound sets a limit that remains at different CMOS processes. On the other hand, the analog bounds for speed and linearity are functions of the device dimensions and parasitic capacitances, and therefore, they scale with technology. An expression for the common-node voltage in the differential current cell structure to achieve minimum analog power consumption is also derived. The expression is found to depend on design and technological parameters, including the differential output voltage swing, the ratio between the commonmode voltage in the differential current cell and the drainto-source voltage of the switch transistors, and the technological noise constant, c.
As technology scales down, the noise energy bound takes over as the parasitic capacitances in the device are reduced, decreasing the energy bounds for speed and linearity. From the comparison with measured data, a narrow gap between the noise energy bound is observed, whereas for the speed energy bound, it becomes larger than one order of magnitude. For the linearity energy bound, there is still some margin with respect to the measured results, which suggests that it is possible to reach even lower energy consumption.
Funding Open access funding provided by Linköping University.
Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons. org/licenses/by/4.0/. His research interests include various issues in design of integrated circuits and systems in advanced nano-scale technologies, with special focus on data converters, sensor readout and data acquisition systems, energy-harvesting and power management systems, low-power wireless sensors, and high-performance digital/ analog baseband and RF frontends for multi-Gigabit/s radio transceivers. He has published more than 100 papers in international journals and conferences, and holds 24 U.S. patents. He is a senior member of IEEE, and has served as a member of technical program committees for many IEEE and other international conferences, including the IEEE Solid-State Circuits Conference, ISSCC, and the European Solid-State Circuits Conference, ESSCIRC. He has also served as guest editor for IEEE Journal of Solid-State Circuits.