Analysis of strong-arm comparator with auxiliary pair for offset calibration

This paper analyzes the principle of the input-referred off calibration using the auxiliary pair for Strong-Arm comparator as well as its impact from the additional common-mode current and parasitic capacitance on the input-referred noise, offset, and decision time in detail. The comparison with the simulation results demonstrates the accurate prediction with the proposed analysis. This paper also discusses the design guideline to optimize the Strong-Arm comparator with the auxiliary pair for offset calibration.


Introduction
The latched comparator is one of the key building blocks of analog-to-digital converters (ADCs). For example, with the requirement of ADC being highly accurate and operating faster with improved power efficiency, the embedded comparator is required to be low power, less delay, higher precision, lower noise, and so on. As the Strong-Arm comparator can achieve fast speed and low power consumption with a simple structure, it is widely used in recent studies. The offset of the comparator in a single-channel SAR ADC mainly due to the process variation will simply cause a shift in the ADC transfer function. In the ADC with multiple comparators embedded in, on the other hand, the offset can impact the effective resolution as it degrades the DNL of the ADC. There are several methods to minimize the effect of the comparator offset.
A conventional method is to design redundancy [1]: a bank of comparators based on different reference levels is designed. One of them with the minimum offset after the fabrication will be activated and used in ADC. In [2,3], combinational redundancy exploits inherent random variables to satisfy the requirement of the matching of transistors to increase the yield of the comparator. A similar idea from [4] is to digitally control the selection of the input transistor pair based on the detection of offsets due to different input transistor pairs applied. The weakness of these techniques is that the rest non-ideal comparators cost too much area. Thus the built-in calibration capability is almost always employed. By adjusting the load capacitance of the comparator, an offset generated by the adjustable capacitance is tuned to have the same amount but opposite polarity with the offset caused by process error [5]. This calibration requires many capacitor arrays to cover a sufficient range, thus requires a large chip area and increases energy consumption per comparison [6]. These large capacitors will significantly reduce the comparator operating speed. The unbalanced clock is introduced to compensate for the input-referred offset voltage caused by the process error by adjusting the clock signal [7][8][9]. Several clock signals (i.e., three clocks in [7,8]) greatly increase the complexity of chip design. The body voltage of the input transistor pair is controlled to tune the current to compensate for input-referred offset [10]. However, it requires a special process to have enough calibration range and resolution.
The Strong-Arm comparator with offset calibration using auxiliary pair is often used in practical designs [11][12][13]. It has the advantages of simple circuit structure, tiny additional load capacitance, zero static power consumption, etc. To the best of the authors' knowledge, there is no paper systematically analyzing this design at present. Hence, in this paper, we mathematically model the Strong-Arm comparator's operating principle and reveal how the auxiliary pair calibrates the input-referred offset as well as affects input-referred noise and decision time. We introduce a guideline to help designers size the auxiliary pair and predict the comparator's performance based on the analysis. Then a practical example is given to facilitate the guideline for the optimized design.
2 Performance analysis of strong-arm comparator Figure 1 shows the structure of a Strong-Arm comparator with auxiliary pair. The operating principle of a Strong-Arm comparator is divided into four phases according to the working states of the transistors, which are resetting, sampling, propagation, and regeneration phases [5].

Without auxiliary pair
A performance of the Strong-Arm comparator without the auxiliary pair is analyzed in detial in [5]. We first outline the analysis in [5], in order to extend it to the circuit with the auxiliary pair. Figures 2 and 3 show the common-mode and differential-mode currents flowing in the Strong-Arm comparator with auxiliary pair for offset calibration during the sampling and propagation phases, respectively. The capacitor pair C C is the parasitic capacitance at the drains of M1 and M2, and capacitor pair C L is the parasitic capacitance at the output ends. The voltages on C C1 and C C2 are denoted as V cn and V cp , and the voltages on C L1 and C L2 are V outn and V outp , respectively. During the resetting phase, CLK is low to precharge the capacitor pair C C and C L to the supply voltage V DD . When CLK goes high, the comparator starts its decision process. The rest three phases are detailed in the following subsections.
The blue lines and the red lines in Fig. 2 represent the common-mode currents (I ic , I calc ) and the differential-mode currents (i id , i cald ) through M1,2 and M7,8 during the sampling phase, respectively. Referring to [5], when there is no auxiliary pair, M7,8 disconnected, the common-mode and differential-mode currents, I ic and i id , are given by   where g m1;2 is the transconductance of M1,2, V cm and v id are the common-mode and differential-mode input voltages, respectively. The tail switch S1 is assumed to operate in the triode region so that V S1 % 0V. V tN is the threshold voltage of NMOS transistor. During the sampling and propagation phases, M1 and M2 are supposed to operate in the saturation region.

Decision speed
As shown in Fig. 4, V cp and V cn drop from V DD to V DD À V tN during the sampling phase, and then drop to V DD À V tN À jV tP j during the propagation phase. V outp and V outn remain at the same value during the sampling phase, and then drop from V DD to V DD À jV tP j during the propagation phase.
During the sampling phase, the common-mode current discharges load capacitance C C . The time window of the sampling phase is given by Then, in the propagation phase, the common-mode current discharges load capacitance C C and C L , the time window of the propagation phase is given by where V tP is the threshold voltage of PMOS transistor.
In the regeneration phase, the differential-mode output voltage integrated during the sampling and propagation phases exponentially increases to V DD , the time window is given by where s reg % C L =g m5;6 , A v is the differential-mode input-to-half-output gain of the comparator without the auxiliary pair [14], which is given by where s p is the time constant in the propagation phase, which is given by The total decision time is given by the sum of time windows of three phases:

Input-referred noise
In the Strong-Arm comparator, based on the analysis in [5], the power of output noise at the end of the propagation phase is composed of two parts: the integration of thermal noise PSD across C L pair in the propagation phase, and the noise across C C pair integrated during the sampling phase transmitted to C L pair. Then, the input-referred noise v 2 n;in is given by where S in ¼ S in1 þ S in2 ¼ 8kTcg m1;2 is the total noise current PSD from the differential input pair, where S in1 and S in2 are the noise current PSD in M1 and M2 respectively. k is the Boltzmann constant and c is a process-dependent parameter.

Introduction of auxiliary pair
In practice, due to the process variation, a differentialmode current through M1 and M2 will be generated during the sampling and propagation phases even with two equal input voltages. Hence, after a while, the voltage drops on the load capacitor pairs are not equal. The unequal load capacitor pairs C C and C L will also unbalance the comparator. The positive feedback loop of the regeneration phase will enlarge the differential-mode output, and then the comparator will generate the wrongly latched output. This undesired output can be regarded as from that the input-referred offset produces a differential-mode current i os to unbalance the ideal Strong-Arm comparator. The auxiliary pair M7 and M8 can be introduced to ensure that the differential-mode output after pre-amplification keeps zero when there is no differential-mode input. It introduces the additional common-mode discharging current I calc as shown in Figs. 2 and 3 with the blue line through M7,8. Besides, it also brings the additional parasitic capacitance.
For the convenience of analysis, we have two assumptions: (a) The voltage drops on switches S1, S2, and S3 as shown in Fig. 1 are equal, i.e. V S1 ¼ V S2 ¼ V S3 , and small enough. In other words, these switches are operating in the deep triode region. (b) The common-mode input voltages on M7,8 and M1,2 are equal, i.e. V calc ¼ V cm ¼ V DD =2.

Additional common-mode current
As stated above, the auxiliary pair will introduce an additional common-mode discharging current I calc during the sampling and propagation phases. The increased discharging current will reduce the time windows of the sampling and propagation phases. Based on the assumptions (a) and (b), the operating statuses of M1,2 and M7,8 are the same. Similar to I ic , the additional common-mode current I calc from the auxiliary pair M7,8 is given by I calc and I ic jointly affect the key performance of the comparator. Since M7 and M8 are supposed to operate in the saturation region in the pre-amplification phase, the increment ratio of the common-mode current r is given by where b 1;2 ¼ l Á C ox Á W 1;2 =L 1;2 and b 7;8 ¼ l Á C ox Á W 7;8 = L 7;8 . C ox and l are the oxide capacitance per unit area and surface mobility of the carrier.

Additional differential-mode current
The auxiliary pair generates an additional differentialmode current to compensate for the contribution from the offset current to the output. Similar to the i id derivation, the differential-mode current i cald through M7,8 is given by Therefore, when a comparison starts, the total differentialmode current unbalancing the circuit becomes i id þ i os þ i cald .

Additional load capacitance
As explained in the previous sections, the capacitance C C and C L are the key parameters that determine the performance of the Strong-Arm comparator. Here we first analyze C C and C L in the different phases for the Strong-Arm comparator without auxiliary pair. During the sampling phase, M3 and M4 are off. For the left half circuit of the comparator, the capacitance C C1 is composed of the parasitic capacitance from M1, M3, and S6. All the parasitic capacitance is related to the width but can be assumed to be independent of the length of the transistors. Hence, the total capacitance from M1 is approximately expressed as c pc Á W M1 , where c pc represents parasitic capacitance per unit width, which is fixed by the process technology. Similarly, the total parasitic capacitance from M3 and S6 is given by c pc Á W M3 and c pc Á W S6 respectively, where W S6 is the width of switch S6. Thus, during the sampling phase, C L1 is isolated by M3, C C1 of the comparator without the auxiliary pair is given by During the propagation phase, M3 and M1 operate in the saturation region. Thus, C C1 of the comparator without the auxiliary pair still approximates Since the output of the comparator is always followed by an inverter, C L1 of the comparator without the auxiliary pair is composed of the drain-gate parasitic capacitance of S4, M3, M6 and a following CMOS (inverter), which is given by where W inv;p and W inv;n are the channel widths of the PMOS and NMOS of the inverter. C L remains at the same value in the regeneration phase, while C C does not affect regeneration.
The introduction of the auxiliary pair will add additional load capacitance to C C , which is from the parasitic capacitance of the additional transistors M7 and M8. It is again given by c pc Á W M7 . Hence, the updated capacitor pair C 0 C1;2 with the introduction of the auxiliary pair is given by which is increased by 1 þ W M7;8 W M1;2 þW M3;4 þW S6;7 times compared with the original one. We define the increase ratio as g, which is given by On estimating C L , it is evident that the auxiliary pair does not affect C L . Hence, C L keeps constant with the introduction of an auxiliary pair.

Decision speed with auxiliary pair
The time window of the sampling phase of the comparator with auxiliary pair is the period that the capacitor C C being discharged by the common-mode current through the input differential pair I ic as well as the common-mode current through the auxiliary pair I calc until the voltage on C C drops by a V tN . Then the time window in [5] is rewritten as: The sampling phase time window of the comparator with auxiliary pair compared with the case without an auxiliary pair is changed by g=r times due to the additional commonmode current and capacitance. Similarly, the time window of the propagation phase of the comparator with auxiliary pair T 0 p is the period of that the capacitors C 0 C and C 0 L being simultaneously discharged by I ic and I calc until the voltage on C 0 L drops by a jV tP j. The auxiliary pair has no impact on C L , thus C 0 L ¼ C L . Supposing that M1,2 and M7,8 operate in the saturation region, the time window for the comparator with auxiliary pair, T 0 p , is rewritten as: During the regeneration phase, the differential-mode output voltage of the comparator with auxiliary pair at the end of the propagation phase, 2V 0 OD , exponentially increases to V DD , similarly as given by (5). The updated time window of the regeneration phase is given by where s 0 reg ¼ s reg since C L is unchanged. By replacing the time windows and the load capacitance in (6) with the values for the Strong-Arm comparator with the auxiliary pair, the updated input-output voltage gain A 0 v is given By deriving this differential input-output gain A 0 v , we can quickly obtain the differential-mode output of the comparator with the auxiliary pair at the end of the propagation phase 2V 0 OD and the time window of the regeneration phase T 0 reg given by (19). The total decision time is the sum of time windows of three phases: According to (17), (18) and (19), the change in the total decision time due to the introduction of the auxiliary pair is given by With the auxiliary pair, the time windows of the sampling and propagation phases usually decrease. In contrast, the time window of the regeneration phase increases since V 0 OD is reduced from V OD with the introduction of the auxiliary pair as explained in the next subsection. Since g m7;8 is normally small enough compared with g m1;2 (r % 1), the reduction of time windows of the sampling and propagation phases dominates the change in the total decision time. When g m7;8 becomes larger (r increases), the increment in the time window of the regeneration phase starts to dominate the change of the total decision time. In practice, however, we do not see the increment since T s þ T p is often multiples of s p . The decision time starts to increase when r is larger than 2. This means that the g m of the auxiliary pair is larger than that of the main differential pair according to (11), which is not reasonable for our purpose to calibrate the offset caused by M1 and M2.

Calibration sensitivity and range with auxiliary pair
The total differential-mode current unbalancing capacitor pairs is updated to i id þ i os þ i cald . The calibration guarantee the sum of the different-mode output voltages integrated by i os and i cald to be zero. Based on the assumptions (a) and (b) given at the beginning of this section, the process is approximated to make i os þ i cald ¼ 0. According to i cald ¼ 1 2 Á g m1;2 Á v os;cal , we refer the differential-current i cald to the differential input pair to give the offset calibrated by the auxiliary pair, which is v os;cal . We define the ratio between the calibrated offset and the differentialmode input voltage to auxiliary pair as the calibration sensitivity, which is given by The calibration range determines the maximum input-referred offset that the auxiliary pair can compensate. According to the calibration sensitivity a given by (23), the calibration range can be determined if we determine the input range for the auxiliary pair. All the analysis above is based on the assumption that M1,2 and M7,8 operate in the saturation region during the pre-amplification phase. The allowable input range for M7 and M8 is V tN þ V S2;3 \V calp;n \V DD À jV tP j. Supposing that the common-mode input voltage is V cm ¼ V DD =2, the allowable input range for M7 and M8 is limited to V tN þ V S2;3 \V calp;n \V DD À V tN À V S2;3 when we assume jV tP j ¼ V tN . Then the calibration range is derived as: The change in C C and C L leads to the change in the integration time window, which has the same impact on the auxiliary pair and the main input transistor pair. Thus, the calibration sensitivity is independent of the load capacitance C C and C L . As a result, the change of the parasitic capacitance does not change the calibration sensitivity. The calibration range AEv os;cal;max is determined by a, as well as the input range to the auxiliary pair V cm À ðV tN þ V S2;3 Þ which is also independent of C C and C L , as given by (24). Thus, the change in the parasitic capacitance does not change the calibration range, either. The input voltage to the auxiliary pair is usually generated from a digital-analog-converter (DAC). The calibration resolution equals the product of the calibration sensitivity and the DAC resolution. Since a is usually small, there is no strict requirement for the DAC resolution. Though the auxiliary pair itself has an additional offset, this offset can also be referred to the differential input pair by sensitivity a, and then calibrated by the auxiliary pair itself.

Input-referred noise derivation with auxiliary pair
With the introduction of the auxiliary pair, by replacing the noise current PSD and time windows in (9) with the values for the Strong-Arm with the auxiliary pair, the input-referred noise voltage is given by From (25), we can see the following: (a) When C C =C L ( 1=2, T s ( T p . Then the additional parasitic capacitance almost has no effect on the input-referred noise voltage. (b) When C C =C L % 1, 2T s % T p . Then the additional parasitic capacitance reduces the input-referred noise voltage by ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 4=ð3 Á g þ 1Þ p times. (c) When C C =C L ) 2, T s % T p ) s p . Then the additional parasitic capacitance reduces the input-referred noise voltage by ffiffiffiffiffiffiffi ffi 1=g p times.

Simulation results
To demonstrate the feasibility of the analysis, the prototype Strong-Arm comparator circuit is designed in 28nm FD-SOI technology, whose nominal supply is 1V. W and L of each transistor in the circuit are summarized in Table. 1.

Decision time dependence on input voltage
Figure 5(a) shows the decision time dependence on the common-mode input voltage V cm applied on M1,2 and M7,8 while v id and v cald are fixed to 0.5mV and 0mV, respectively. The increment of the common-mode input voltage leads to a larger discharging current that speeds up the comparator decision. The time windows of the sampling and propagation phases decrease with the trend of the function 1=V cm , which is given by (8).
We then fix the common-mode input voltage V cm to V DD =2 ¼ 0:5V and sweep v id from 0.5mV to 4mV while v cald is kept 0mV as shown in Fig. 5(b). Even with the increased differential-mode input voltage v id , the time windows of the sampling and propagation phases stay almost constant, while the time window of the regeneration phase decreases due to the increment of differential-mode output at the end of the propagation phase. The downward trend corresponds to Àlnðv id Þ, which agrees with (19).   120nm to 1:2lm while L M7;8 is fixed to 90nm. v id and v cald are 0.5mV and 0mV respectively. Analysis considers both additional current and parasitic capacitance based on (21). When we take the additional capacitance into account, with the increment in W M7;8 , increasing g and r ¼ 1 þ a jointly determine the decision time according to (17) and (18), then the curve becomes flatter to have better agreement with simulation, as shown in Fig. 6. Figure 7 shows the sensitivity a dependent on b 7;8 =b 1;2 . Circles show the simulation results when W M7;8 =L M7;8 is fixed to 240nm=90nm, while W M1;2 =L M1;2 is fixed 9lm=45nm in triangle case. Our analysis in (23) gives a good prediction of the sensitivity. The discrepancy when a becomes larger is explained by two reasons:

Calibration sensitivity
(a) The unequal voltage drops between S1 and S2,3 will change the sensitivity. (b) The auxiliary pair can not generate sufficient compensating current as expected since M7 and M8 can go into the triode region before the regeneration starts.
When the input transistors operate in the triode region after the regeneration starts, the voltage difference between V S1 and V S2;3 can not be ignored if V S2;3 is larger than V S1 . Thus, the auxiliary pair is not able to generate enough compensating current, which means that the calibrated integrated differential-mode output voltage, in reality, will be slightly smaller than the simplified calculation result. Besides, if b 7;8 increases, it will lead to a larger commonmode current i calc resulting in a larger V S2;3 . The calibrated integrated differential-mode output voltage, in reality, will increase slower along with the increment of b 7;8 . Figure 8 shows the input-referred offset voltage dependent on v cald when transistor sizes are fixed as summarized in Table. 1. The calibrated offset changes linearly with the increment of v cald . When v cald is small, the analysis results precisely agree with the simulation. As jv cald j increases, the slope of the simulation results becomes flatter leading to a discrepancy with analysis results. This is because M7 or M8 starts to operate in the triode region at the boundaries of the allowable input range. Fig. 9(a) shows the input-referred noise simulation result when we keep W/L ratio of the transistors in the circuit constant and scale all transistors simultaneously in the same proportion, which is defined as n. Since increasing sizes of transistors give larger parasitic capacitance considered as load capacitor pairs while keeping the current through the comparator, it leads to larger T s and T p according to (3) and (4). Thus, the input-referred thermal noise voltage decreases with the trend of 1= ffiffi ffi n p according to (9). Fig. 9(b) shows the input-referred noise dependence on a. Firstly, W M7;8 is fixed to 240nm, then L M7;8 is swept from 360nm to 90nm. Secondly, L M7;8 is fixed to 90nm, and W M7;8 is swept from 240nm to 960nm. There are two slopes of the input-referred noise increment along with a. The slope, while decreasing L M7;8 , is larger than the that while increasing W M7;8 . This result is due to the additional capacitance of the auxiliary pair at C C . When we change the length L M7;8 and fix the width W M7;8 , b 7;8 changes, but the parasitic capacitance from the auxiliary pair does not increase, which means g is fixed. Regardless of the ratio of C C to C L , the input noise increases by r ¼ 1 þ a times according to (9). When we fix the length L M7;8 and change the width W M7;8 , on the other hand, b 7;8 increases while the additional parasitic capacitance from the auxiliary pair also increases. The increment in capacitance leads to a narrower bandwidth limiting thermal noise PSD integration, thereby Simulation Analysis (Eq. 23) Fig. 8 Input-referred offset voltage dependent reducing the input-referred noise. Hence, the increment of the additional capacitance suppresses the increment of input-referred noise caused by r. The complete change of input-referred noise voltage is related to the ratio between C C and C L as given by (25).

Design guideline
The analysis given in this paper can help to design a Strong-Arm comparator with auxiliary pair by intuitively predicting its performance and calibration ability with simple mathematical equations. Suppose that we will add an auxiliary pair to calibrate the input-referred offset of the Strong-Arm comparator. The introduction of the auxiliary pair adds the input-referred noise. Besides, depending on the a and g, the decision time of the comparator may change. There are tradeoff relationships among the calibration range, decision time, and input-referred noise to determine the size of the auxiliary pair. For instance, if we need a wider calibration range, a larger g m7;8 is needed according to (23) and (24). It leads to more input-referred noise according to (25). Also, the additional parasitic capacitance increases the power consumption but reduces the decision time by reducing T s and T p . To insert a suitable auxiliary pair to calibrate the Strong-Arm comparator, we need to optimize its size by determining the values of a and g. We first need to know the desired calibration resolution and the minimum voltage step from the digital-to-analog converter (DAC) to the auxiliary pair to determine the maximum calibration sensitivity a. Then, we can determine the minimum a with the required calibration range. Based on the requirements of decision time and input-referred noise, we can decide g. Finally, W M7;8 and L M7;8 are determined.

Parameter setting process
As one of the practical examples, we start with a Strong-Arm comparator without the auxiliary pair whose transistor sizes are summarized in Table. 1 except M7, M8, S2 and S3. Its input-referred noise voltage, decision time (while v id ¼ 0:5mV) and input-referred offset are 0.475mV, 44ps and r ¼ 0:5mV, respectively. jV tP j ¼ V tN ¼ 0:2V is used for the threshold voltage. Then we are required to add an auxiliary pair by finding the optimum size of M7,8 to satisfy the metrics listed in Table. 2. Here we suppose that the voltage applied to the auxiliary input is ideal and noiseless. Although the variation and noise on the auxiliary input affect the performance of the comparator by introducing the fluctuations on both the differential-and common-mode currents, according to (11) and (23) the impact on the decision time, the input-referred noise and the offset is suppressed by the factor of g m7;8 =g m1;2 , which is usually (1. As it is common to supply the auxiliary input voltage from an on-chip DAC or regulator, we can safely assume that the variation and noise on the voltage are originally small. Thus, in total, its impact on the comparator performance can be negligible. (a) Suppose that we need to calibrate AE3r ¼ AE1:5mV offset, so that the calibration success rate can reach 99:7%. Since the input range to the auxiliary pair is  limited to AEv os;cal;max ¼ AE2 Á ðV cm À ðV tN þ V S2;3 ÞÞ ¼ AE0:6V according to (24) in Sect. 2.4, we can determine the minimum a that meets the calibration requirements, which is a ! 3r=v os;cal;max % 1=400. Hence, we are able to get the allowable minimum of b 7;8 from a ¼ b 7;8 =b 1;2 in (23) while b 1;2 is given. In practice, we need to leave a certain margin since the auxiliary pair itself is also affected by the process variation.
A larger a is always accompanied by lower calibration resolution when the input voltage to the auxiliary pair comes from the embedded DAC whose minimum voltage step is limited. When the required calibration resolution is r=16 ¼ 0:03125mV supposing that the minimum step voltage of the embedded DAC is 1mV, a 0:03125 ¼ 1=32. (b) When introducing the auxiliary pair, we need to accept a certain amount of additional noise as given by (25). With a fixed a, a larger g can suppress the increase of the input-referred noise but slow down the decision. If the input-referred noise voltage is allowed to increase v times compared with the original one, according to (25), when (c) Regarding the decision time, we know that the change in the decision time is dominated by the change of the time window of the pre-amplification phase, as explained in Sect. 2.3 . According to (17) and (18), whether the time window of the preamplification phase increases or decreases depends on whether rg is greater or smaller than 1. We prefer not to increase the decision time of the comparator which means rg ¼ g=ð1 þ aÞ 1. Hence, g ð1 þ aÞ.
Then, when we are allowed to increase the input-referred noise 1%, i.e., v ¼ 1:01, we are able to obtain a 1=62

Performance prediction
From W M7;8 =L M7;8 ¼ 240nm=90nm, we can use a ¼ 1=75, r ¼ 75=76 and g ¼ 101=100. Since in this example C C =C L \1 but C C is not much smaller than C L , we can predict the key performances of the comparator compared with the original one through two models: C C =C L ( 1=2 and C C % C L . (a) The time window of the pre-amplification phase is reduced by 0:1ps $ 0:3ps, while the time window of the regeneration phase keeps almost constant. From the simulation results in Fig. 6, the decision time drop is 0.2ps when a ¼ 1=75. (b) The input-referred noise is predicted to increase to 0:481mV $ 0:487mV. From the simulation results in Fig. 9(a), the input referred noise is 0.482mV. (c) The calibration range can reach AE8mV without considering the margin. From the simulation results in Fig. 8, when v cald reaches V calp À V valn ¼ 0:6V, the calibrated offset reaches 6.9mV. The discrepancy is 1.1mV compared with the expected value 8mV. It is because the actual V tN and jV tP j are slightly larger than 0.2V. (d) The calibration resolution can reach 1=75mV ¼ 2r=75 which agrees with the simulation results shown in Fig. 8.
Sometimes we may not find an intersection region based on decision time and input-referred noise voltage requirements. Then, we need to relax the specifications. For instance, we may need to allow the comparator more decision time to increase the maximum limitation of g. Or we may need to allow more input-referred noise, while increasing v will reduce the minimum limitation of g. By following the above design procedure, we have the optimum W M7;8 and L M7;8 with a minimized performance penalty.

Conclusion
This paper systematically analyzes the operating principle of the Strong-Arm comparator with offset calibration using the auxiliary pair. Through simplified equations, the calibration principle and ability of the auxiliary pair are accurately predicted. The impact of the auxiliary pair, including additional current and parasitic capacitance, on the decision speed and input-referred noise is analyzed with these equations. The designers can find the optimum size of the auxiliary pair in the Strong-Arm comparator by determining the values of a and g defined in the analysis, which can be efficiently derived according to their design requirements. A practical example is given to facilitate the guideline for the optimized design.