Load-dependent power transfer efficiency for on-chip coils

This paper presents a theory for the power transfer efficiency of printed circuit board coils to integrated circuit coils, with focus on load-dependence for low-power single-chip systems. The theory is verified with electromagnetic simulations modelled on a 350 nm CMOS process which in turn are verified by measurements on manufactured integrated circuits. The power transfer efficiency is evaluated by on-chip rectification of a 151 MHz signal transmitted by a spiral coil on a printed circuit board at 10 mm of separation to an on-chip coil. Such an approach avoids the influence of off-chip parasitic elements such as bond wires, which would reduce the accuracy of the evaluation. It is found that there is a lower limit for the load below which reducing the power consumption of on-chip circuits yield no increase in voltage generated at the load. For the examined process technology, this limit appears to lie around 56 kΩ\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\Omega$$\end{document}. The paper is focused on the analysis and verification of the theory behind this limit. We relate the results presented in this work to the application of wireless single-chip temperature monitoring of power semiconductors and conclude that such a system would be compatible with this limit.


Introduction
On-chip coils for wireless power transmission can be used to enable battery-free operation for integrated circuit systems such as implantable chips in humans [1][2][3][4] as well as for galvanically isolated, direct-contact temperature sensors for condition monitoring of power semiconductors [5,6]. For integrated circuits powered by on-chip coils, it is important to achieve a sufficiently high power transfer efficiency (PTE), so that on-chip sensors' power requirements can be met without an excessive amount of power being consumed at the transmitter. However, the small dimensions of an on-chip coil limit its ability to draw energy from a magnetic field generated by a transmitter coil. Another limiting factor for the PTE is the typically low Q factors for such coils, resulting in a large amount of resistive losses occurring in the coils. For example, Zargham and Gulak [1], Feng et al [2], and Khalifa et al [3] demonstrate on-chip coils with Q factors of 11.05 at 101 MHz, 10.5 at 450.3 MHz, and 10.8 at 2.0 GHz, respectively. This is in contrast to printed circuit board (PCB) coils for which it has been demonstrated that their Q factors can exceed 100-or even 400 if advanced PCB substrates are employed [7].
One additional challenge is the load requirements and the limitations imposed by the associated on-chip matching network. Because integrated circuit (IC) inductors with large inductance are difficult to manufacture with high Q factors, the matching network typically consists only of capacitors. Therefore any inductive part required by a matching network has to come from the on-chip receiver (Rx) coil. Because large load resistances require large inductors in order to be matched to the coil impedance, attempting to reduce the power consumption by reducing the load becomes ineffective beyond a certain point.
In this paper, we analyse the power transfer efficiency of systems powering on-chip coils with emphasis on the implications light loads (large load resistances) have on coil design. Focus is put on the implications for the power requirements of the transmitter. We evaluate the PTE by providing simulations for coil designs optimised for different loads and frequencies. In order to verify the simulation model, results of measurements are presented from an IC with an on-chip coil operating at 151 MHz, complete with a simple single-transistor half-wave rectifier. The onchip rectification approach enables accurate measurements to be made at the Rx side because off-chip parasitic elements such as bond wires, probes and breakout trackswhich can be very significant at the frequency in question-are made irrelevant because off-chip currents are direct current (DC).
We assess the usefulness of the results presented in this work by relating them to the application of using wireless single-chip sensors to monitor the temperature of power semiconductors in a power semiconductor module, originally proposed in [5]. A schematic view of the proposed monitoring system is shown in Fig. 1. Single-chip temperature sensors with on-chip coils are glued in direct contact with the power semiconductors to provide accurate temperature measurements in order to predict emerging faults. The sensors are powered by and communicate with printed spiral coils (PSCs) located on a PCB on top of the power semiconductor module. The wireless interface provides galvanic isolation between IC sensors and a system controller located on the PCB outside the module housing. Monitoring of temperature can be used to predict solder fatigue [8], bond wire lift-off [9] or be a part in predicting emerging semiconductor faults [10,11]. According to a 2007 study, these faults account for 34% of total failures in power electronic equipment [12].
The paper is organised as follows. In Sect. 2, we present an overview of how the power transfer efficiency is evaluated, including the measurement set-up and the placement of the different coils. In Sect. 3, we detail the circuits used to model the coils and derive a theoretical limit for when the required transmitter power does not decrease even if the power consumption at the load is reduced. Section 4 presents simulations of optimised coil geometries supporting the theory. These simulations are verified by measurements on manufactured devices and the results of the measurements are presented in Sect. 5. Conclusions are presented in Sect. 6.

System overview
In this section, we describe the measurement set-up used to evaluate the power transfer efficiency between two coupled coils: a transmitter (Tx) spiral coil printed on a PCB and an Rx spiral coil printed on an IC chip utilising a 350 nm complementary metal-oxide semiconductor (CMOS) process. The measurements are used to verify the simulation model presented in Sect. 4. Both Tx and Rx coils are PSCs characterised by outer dimension, d X ; trace width, W X ; trace separation, S X ; and number of turns, N X . Here, X denotes either the receiver coil, Rx, or the transmitter coil, Tx. These parameters are illustrated in the schematic diagram of Fig. 2. The power transfer efficiency is evaluated at a coil separation of D ¼ 10 mm, which is a reasonable distance both for biomedically implanted chips [1] and for sensor chips for condition monitoring of power semiconductors [6].
An overview of the measurement set-up is shown in Fig. 3. The excitation signal is generated using a Prâna APT32MT225 Power Amplifier driven by a sinusoid which is generated by an Agilent E8267D Signal Generator. The power signal is attenuated by 6 dB by a power attenuator and the attenuated signal is fed to a Mini-Circuits ZFBDC20-62HP-S? directional coupler from which À20 dB is coupled to and measured by an Anritsu ML2437A power meter. The output of the coupler is fed to a PCB with the Tx coil. Any reflected power from the PCB is fed back to the directional coupler from which À20 dB is coupled to another ML2437A power meter. Using the two power measurements, the power, P S , delivered to the PCB can be calculated. Fig. 1 Schematic view of the cross-section of a wire-bond power semiconductor module whose devices are being monitored by singlechip temperature sensors powered by printed spiral coils mounted on top of the module Fig. 2 Schematic diagram of a printed spiral coil. Shown are the geometry parameters, tracewidth, W; trace separation, S; outer diameter, d; and number of turns, N used to describe its geometry An inductive link is formed by the two coils, and a fraction of the signal power fed to the Tx coil is coupled to the Rx coil. In the following, this system is described in more detail:

Transmitter printed circuit board
On the Tx side, a PSC is printed on a PCB with a discrete LC matching network to enable sufficient power to be delivered to the Tx coil at the operating frequency. The matching network consists of a series variable capacitor and a shunt inductor. Because of the low equivalent series resistance (ESR) of the transmitting coil, losses in the matching components may be significant.

Receiver chip
On the Rx side, a PSC is printed on a 2 Â 2 mm 2 IC chip using the two top metal layers. Because large on-chip inductors require large area and typically exhibit low Q factors, the matching network consists of a single onchip shunt capacitor, which forms a resonant circuit with the Rx inductor.
The integrated circuit includes a single-transistor halfwave rectifier, the purpose of which is to increase the accuracy of the measurements by rectifying on-chip and thus making the system less sensitive to parasitic effects. Such effects include magnetic coupling from the Tx coil to bond wires and PCB tracks as well as parasitic capacitance between such elements and within coaxial cable connectors. The simplicity of a single-transistor rectifier enables accurate estimation of its power consumption. It is thus possible to separate the power consumed in the rectifier from the power, P L , consumed in the load, obtaining estimations of both.
Excluding the IC coil which runs along the chip's perimeter, the rectifier consumes 54 nm 2 of silicon area. The total area consumed by the coil amounts to 346 nm 2 :

Inductive link and rectification
A circuit diagram of the two coupled Tx and Rx coils is shown in Fig. 4 complete with matching networks, rectifier and load. An inductive link is formed between the Tx coil, L Tx , and the Rx coil, L Rx , coupled by the mutual inductance, M. L m,Tx and C m,Tx constitute the matching network on the Tx side while the single shunt capacitor, C m,Rx , constitutes the matching network on the Rx side. The metal-oxide semiconductor field effect transistor (MOSFET), M D , is configured as a PMOS diode which rectifies the voltage induced in L Rx . The rectified energy is used to drive a load resistor, R L , external to the chip. Energy not consumed in the load is stored in the energystorage capacitor, C E , and used to drive the load when M D is reverse-biased. Also shown is the equivalent resistance, R 0 L , due to the average loading of coil with matching network, which is the sum of R L and the average Fig. 3 Overview of the measurement set-up used to verify the electromagnetic model used for simulations. A sinusoidal E8267D signal generator drives a APT32MT225 power amplifier. The signal is then attenuated by 6 dB and the attenuated signal is fed to a ZFBDC20-62HP-S? directional coupler from which À20 dB is coupled to and measured by an ML2437A power meter. The output of the coupler is fed to the PCB Tx coil and any reflected signal is fed back to the directional coupler and À20 dB of the reflected signal is measured by another ML2437A power meter. Power is transferred inductively from the PCB Tx coil to the IC Rx coil where the signal is rectified and fed to a load. The voltage at the load is buffered by an ADA4505 operational amplifier in voltage follower configuration and then sampled by an MSOX2024A oscilloscope equivalent resistance of the rectifier. The DC value of the load voltage, V L , is buffered by an Analog Devices ADA4505 operational amplifier in voltage follower configuration and then sampled by an Agilent MSOX2024A oscilloscope. With the sampled voltage, the power, P L , consumed at the load can be estimated.

Coil modelling and design
In this section we describe the electromagnetic situation for the monitoring system shown in Fig. 1. A theory is presented demonstrating the effect that the loading of the onchip coil has on transmitter power consumption. We argue that decreasing the load (that is increasing the load resistance) beyond a certain point has a negative impact on the power transfer efficiency which precisely cancels out the positive effect of a lower current consumption at the load. The result is that, beyond this point, the transmitter power required in order to realise a constant voltage at the load does not decrease even if the load is reduced.
In Sect. 4, we present simulation results to support the theory. These results are obtained from an optimisation algorithm that uses an electromagnetic simulator that generates optimised coil-designs for varying loads and frequencies.

On-chip coil circuit model
The on-chip coil is modelled as in Fig. 5. Here, V emf ðjxÞ is the electromotive force (emf) voltage phasor induced in the Rx coil from the magnetic field generated by the Tx coil. L Rx is the coil inductance and R Rx is the ESR of the coil due to the combined effects of non-zero resistance of the metal constituting the coil and due to resistive losses in the silicon substrate due to induced substrate current (and current induced in a substrate shield). C sub and R sub represent equivalent capacitance and resistance due to capacitive coupling to the ground-connected conductive substrate while C turn represents the equivalent capacitance between turns. This is a simplified model whose purpose is to yield design insight of how the coil geometry affects the properties of the final coil.
The dependencies of the Rx model parameters, V emf , R Rx , L Rx , R sub , C sub and C turn on the Rx geometry parameters, W Rx , S Rx and N Rx are summarised in Table 1. Here, V emf is the amplitude of the emf voltage phasor, V emf ðjxÞ.
Here, ''-'' denotes no or insignificant dependence, % denotes a function that increases with the geometry parameter, while & denotes a decreasing relation For thin, long conductors, the inductance increases with the logarithm of W Rx [13], while the ESR decreases inversely proportionally to W Rx . The skin effect is assumed negligible because of the small thickness of the IC metal layers. Because of the increase in total surface-area consumed by the coil, increasing W Rx results in that the coil will be capacitively coupled to a larger fraction of the substrate, decreasing R sub and increasing C sub . S Rx has a similar effect on R sub and C sub due to increasing coil area, while also decreasing the inter-turn capacitance roughly inversely proportionally to S Rx . N Rx increases the induced emf voltage in the coil roughly linearly [14], while the coil inductance increases roughly proportionally to the square of N Rx [15]. We say roughly because the diameter of each turn is not uniform for a printed spiral coil, nor is the coil circular and hence the assumption of an ideal coil is an approximation. Because the inner turns will attain smaller diameters if either W Rx or S Rx is increased, V emf will decrease slightly for such a case. Additionally, increasing N Rx adds a roughly linear term to the ESR because the coil gets longer roughly proportionally to the number of turns. Furthermore, because the inductive coupling to substrate or substrate shield increases with the square of the number of turns [16], another term, N 2 Rx , is added to R Rx . It is assumed that the optimised coil geometries will have values for the turn separation of the Rx coil, S Rx , that makes the effect of the inter-turn capacitance on the power delivered to the load small and thus, this effect is ignored henceforth. Furthermore, we do not attempt to estimate values for C sub and R sub due to the complexity of such a task, but merely discuss the limitations the effect as a whole imposes on the coil design. Thus, for calculations, we assume that the effects of C sub and R sub are represented in V emf ðjxÞ, L Rx and R Rx :

Maximum load resistance
As explained in Sect. 2.2, the on-chip matching network consists of a single shunt capacitor. A series capacitor would cancel out the reactance of the coil, while a shunt capacitor would cancel the coil reactance, but also transform the load resistance into a smaller one. For low-power operation, the load resistance is assumed to be larger than the magnitude of the source impedance given by the ESR of the Rx coil in series with the coil reactance. Thus, in order to bring the load resistance as close as possible to the magnitude of the source impedance-in an effort to maximise the power delivered to the load-the matching network consist of a shunt capacitor, as illustrated in Fig. 4.
To simplify the analysis and without loss of generality, the average equivalent load resistance, R 0 L , is used for calculations.
The power, P L , delivered to the average equivalent load, R 0 L is given by where V emf ðjxÞ is the input voltage phasor generated in the Rx coil by the signal transmitted from the Tx coil, x is the angular operating frequency and Z eq is the equivalent impedance from the parallel connection formed by C m,Rx and R 0 L , given by By substituting Eq. 2 into Eq. 1, it can be shown that P L can be expressed as where V emf is the amplitude of the input voltage phasor, V emf ðjxÞ. It can be seen from Eq. 3 that for a fixed on-chip coil design (fixed values for V emf , R 0 L , R Rx , L Rx and x), in order to maximise P L , the expression should be minimised. Because is positive, yields a local minimum point for xC m,Rx ; namely Inserting Eq. 7 into Eq. 3 yields where where Q Rx ¼ xL Rx =R Rx is the Q factor of the Rx coil. Assuming a reasonably high Q Rx , P L,max in Eqs. (8) and (10) represent the maximum obtainable power for a fixed on-chip coil design assuming an ideal matching capacitor, C m,Rx . A method for manufacturing trimmable, high Q factor IC capacitors which can be utilised in order to approximate such a capacitor has been proposed in [17]. As can be seen from Eq. 9, c will decrease with increasing Q factor. Thus for high Q factors, R 0 L will be less significant for P L,max and in turn for the power transfer efficiency, g ¼ P L,max =P S . Based on observed IC coil Q factors from this and previous works [1,2], for optimised coils, c typically attains values of around 0.6-10 %.
In the following, we will show that the coupled PCB-IC coil system of this paper operates in three different regions of operation characterised by the power consumption at the load. We denote these regions the high-power, mediumpower and low-power regions of operation. The conditions for these regions are illustared in the form of a flowchart in Fig. 6, and the remainder of this section is devoted to analysing their characteristics and conditions.
As noted in Table 1, the induced voltage amplitude, V emf , is roughly proportional to the number of turns in the receiver coil, N Rx , while the inductance, L Rx , is roughly proportional to N 2 Rx . Thus, Eq. 10 shows that increasing N Rx beyond the point where x 2 L 2 =R 0 L starts to become dominant will reduce the maximum power delivered to the load, P L,max . We say that the system transitions from operating in the high-power region to the medium-power region at this point. Due to the previous reasoning, it can thus be assumed that for an optimal coil design, However, it should be noted that this assumption ignores the fact that the number of turns must be a non-zero integer.
The assumption may thus be false for designs with few turns for which the impedance, x 2 L 2 Rx =R 0 L , (the values of which are quantised for a constant R 0 L due to the quantised nature of N Rx ) may be excessively small compared to 2R Rx . Thus for some designs, a unit increment in N Rx would result in an increase in P L,max because, for some cases, the benefit of a higher V emf would actually be bigger than the drawback of a higher x 2 L 2 Rx . Thus for medium-power operation, the approximation given in Eq. 11 is valid, but for for high-power operation, it may be invalid and we should resort to using Eq. 10.
Because x 2 L 2 Rx =R 0 L will dominate the denominator of Eq. 10 only for small values of R 0 L , it is only relevant for high-power operation, which is not the focus of this work. However, it should nonetheless be noted that because Rx =R 0 L is significantly more detrimental for P L,max than is cR 0 L in this region of operation, it would be more beneficial to employ a series capacitor matching network which would fully cancel the coil reactance. The maximum power consumption for series matching network would then be given by Eq. 8, but with c ¼ 1 and xL Rx ¼ 0, that is The drawback here is that the R 02 L term in the denominator of Eq. 8 is no longer reduced by a factor c and thus, if R 02 L is dominant, the power delivered to the load will be reduced, again illustrating that a series-capacitor topology is suboptimal for medium-and low-power operation. Rx =R 0 L will no longer be dominant in the denominator of Eq. 11. Thus, in this region, the more R 0 L is increased, the more N Rx can grow without being detrimental for P L,max . From Eq. 11 and Table 1, it can be seen that a linear increase in N Rx yields a roughly quadratic increase in P L,max due to the resulting increase in V emf . However, R Rx will increase roughly linearly, which is detrimental for P L,max , but is detrimental to a smaller extent than the increase in V emf is beneficial for P L,max . A linear increase in R Rx will also result in a roughly quadratic increase in c due to the Q 2 Rx term in the denominator of Eq. 9. Nevertheless, because of the typically low Q factors of on-chip coils, the unity term in the denominator of Eq. 9 may be significant, resulting in an overall reduction in c that is less than quadratic and which can thus be less detrimental for P L than the quadratic increase in V emf . Therefore, W Rx can decrease slightly, in turn increasing V emf slightly because of the increased radii of the inner turns, without the resulting increase in R Rx consequentially resulting in that 2R Rx becomes the dominant term in the denominator of Eq. 11 and without scaling up c by more than by how much V 2 emf was scaled. A consequence of this behaviour is that, when the power transfer efficiency, g ¼ P L,max =P S , decreases due to increasing R 0 L , the power delivered to the load, P L,max , can still increase (for the same transmitted power, P S ) due to the boosts in V emf resulting from an increased number of turns and increasing diameters of the inner turns due to a smaller trace width. However, there is a limit for the load resistance for when increasing the number of turns, N Rx , will stop being beneficial for P L,max . Because of the diminishing returns in the increase in V emf due to the increasingly smaller radii of the inner turns when an additional turn is employed, and the increasingly limiting effects of the substrate when the fill factor of the coil is increased, beyond this limit, which we denote R L,cutoff , an increase in N Rx will instead be detrimental for P L,max . For values for R 0 L [ R L,cutoff , the strategy of increasing R 0 L in an attempt to move towards lower power operation becomes ineffective because P L,max , and in turn g, are reduced with the same factor as the load current (which is given by V L =R 0 L ). The implication is that, beyond this point, reducing the load current does not significantly increase the available supply voltage, V L , for a given V emf .
When N Rx no longer can be increased, the benefits by a decrease in W Rx seen for medium-power operation will no longer apply and the coil geometry will thus not vary much in the region of low-power operation. Consequentially, in the low-power region, 2R Rx will no longer increase and cR 0 L will be dominant in the denominator of Eq. 11. Therefore, cR L ) 2R Rx and Eq. 11 can be approximated by Because of the coil geometry invariance in the low-power region of operation, a viable strategy for finding R L,cutoff may be to determine the impedance of an optimised coil geometry for a high R 0 L (well into the low-power region), and use the result to calculate values for the impedances cR 0 L and 2R Rx . At the transition from medium-power to low-power operation, 2R Rx will stop being significant, and thus at this point, it can be assumed that 2R Rx will be only slightly smaller than cR 0 L . We denote the fraction that relates cR 0 L to 2R Rx as b. Thus, for low power operation: The cut-off point, R L,cutoff can then be found by substituting R 0 L ¼ R L,cutoff into Eq. 14 and solving for R L,cutoff . R L,cutoff is then given by Towards the end of Sect. 4, we will empirically determine a suitable value for b.

Coil geometry optimisation for varying load
A gradient ascent algorithm was used in conjunction with the electromagnetic simulator FEKO [18] in order to optimise the coil geometries for high power transfer efficiency. The algorithm is the same as from our earlier work [6], based on an algorithm originally presented by Zargham and Gulak [1]. Pseudo-code for the algorithm is repeated for reference in this work in Algorithm 1. For the electromagnetic simulations, an IC chip was modelled in direct contact with a power semiconductor inside a module as shown in Fig. 1. An extended version of the schematic including material information is shown in Fig. 7, while permittivities and conductivities for the materials are listed in Table 2. In order to shorten simulation times, the model was simulated in 2.5-dimensional (2.5D) mode, where the layers of the different materials are modelled as infinite slabs in the horizontal direction. A 350 nm, 3.3 V process (C3B4C3 from ams AG) with 4 metal (copper) layers was used. Out of these layers, the top 2 layers, metal 3 and metal 4 were used for the coil, stitched together with vias at the corners, realising a parallel connection. The bottom metal layer, metal 1, was used to shield the on-chip coil from the conductive substrate [1]. The shield consist of a chopped-up coil laid out directly underneath the Rx coil.
The coil geometries were optimised in order to maximise the power transfer efficiency, g, for different average equivalent load resistances, R 0 L , a coil separation of D ¼ 10 mm and an outer diameter for the Rx coil of d Rx ¼ 2 mm. In order to assess which is the most favourable frequency, simulations were first run in order to optimise g for R 0 L ¼ 100 kX. The frequency bands 44.66, 169.4, 433.0 and 868.0 MHz were examined. These are industrial, scientific and medical (ISM) bands or other frequency bands recommended by the Swedish post and telecommunications authority [19]. Out of these, 169.4 MHz yielded the highest power transfer efficiency at g ¼ À45:5 dB, and so, the remainder of the simulations presented in this section were carried out at this frequency 1 .
To visualise the characteristics of the best values of power transfer efficiency, the coil geometries were optimised to maximise g for various values of R 0 L . The best values found by the optimiser are shown in Figs. 8 and 9, where the power transfer efficiency and its corresponding Rx coil geometry, respectively, are plotted against R 0 L . Also shown are the high-power, medium-power and lowpower regions of operation as described in Sect. 3.2. From Fig. 8 it can be seen that the maximum power transfer efficiency occurs in the high-power region, around R 0 L ¼ 180 X. We comment on the Rx coil dimensions in relation to power transfer efficiency later in this  *Value known and used for simulations, but can not be published due to non-disclosure agreement 1 We should note that this frequency differs from the one obtained in our earlier work; 433 MHz [6]. The reason for this is a previous error in the model which placed the substrate farther apart from the copper traces than it should have been, resulting in underestimated substrate effects. This error has since been corrected and the corrected version is used for the simulations in this work. As a result of the error, the results obtained in our previous work also overestimates the power transfer efficiency. The power transfer efficiencies shown in this work are verified against measurements and are thus believed to be accurate.
section. The optimisation algorithm yielded roughly the same geometry for the Tx coil for all the examined average equivalent load resistances and thus we present its geometry and Q factor for the arbitrarily chosen value of R 0 L ¼ 10 kX in table form in Table 3. The lack of variation is expected due of the weak coupling between the coils which results in that the effect of the loading of the Rx side is not very significant for the Tx coil.
In the following paragraphs, we assume that the optimiser has found near-optimal coil geometries. Figure 10 shows plots of the impedances of the terms in the denominator of Eq. 10 as a function of load resistance. Looking at both the figure and the equation, it can be seen that x 2 L 2 Rx =R 0 L stops being significant for P L,max at around R 0 L ¼ 320 X. Looking back at Fig. 8 it can be seen that it is around this point that g starts to fall off, and at around R 0 L ¼ 56 kX, the maximum decline of 10 dB per decade increase in R 0 L is reached. As argued in Sect. 3.2, it is beyond this point that, for a constant load voltage, there is no reduction in the required transmitter power, P S , even if an attempt to reduce it is made by increasing R 0 L because the current consumption-and hence the power delivered to the load, P L -decrease at the same rate as does the power transfer efficiency, g. This phenomenon can be seen in Fig. 11. Here, both P L and g are plotted as functions of load resistance, and the figure also plots the power consumption of the transmitting coil, P S , required in order to realise a root-mean-square (rms) load voltage, V L , of 1 V. The purpose of presenting plots for constant V L is to uncover the behaviour of P L when the current consumption is solely dependent on load resistance. The figure shows that the required transmitting power decreases up to the point where the plotted slopes of P L and g become equal, at which point P S starts to level off, asymptotically reaching a constant value of around 20 dBm at around R 0 L ¼ 56 kX. It is interesting to analyse Figs. 9, 10 and 11 further. It can be seen that in the region of high-power operation, where R 0 L \320 X, either 2R Rx or x 2 L 2 Rx =R 0 L is dominant and L Rx must be kept low in order to not be detrimental for P L . Because of the strong dependence of L Rx on N Rx , N Rx will be kept low in this region as can be seen from Fig. 9. An exception is R 0 L ¼ 100 X, where it turns out that increasing N Rx by one turn was more beneficial for P L due to the increase in V emf than it was detrimental due to the increase in L Rx . However, when x 2 L 2 Rx =R 0 L is surpassed by both cR 0 L and 2R Rx , L Rx can grow without a reduction in P L and the system transitions into the medium-power region of operation. A consequence is that N Rx starts growing steadily at around R 0 L ¼ 320 X after which Rx =R 0 L never again becomes dominant. N Rx grows until it reaches a maximum of N Rx ¼ 11 where additional turns will be detrimental to P L -due to the diminishing returns in inductance for additional turns and to stronger substrate effects-more than it will benefit P L due to the increase in V emf . Figure 12 shows the Q factors resulting from optimising the Rx coil for different average equivalent load resistances, R 0 L . The figure shows that while the Q factor is relatively high for low R 0 L , it rapidly drops off in the medium-power region of operation and eventually reaches a minimum of Q Rx % 1 when the system reaches the low-   9 Optimised geometry of the Rx coil plotted as a function of average equivalent load resistance. The trace separation is undefined for coil geometries with only a single turn, which is why values are missing for S Rx for load resistances smaller than 100 X power region. This behaviour is expected because the number of turns, N Rx is fairly constant in the high-and low-power regions, while steadily increasing in the medium-power region. A high number of turns will decrease Q Rx because the trace width, W Rx , will decrease to accommodate the additional turns. On top of this, because the inner turns have smaller diameters compared to the outer one, the increase in inductance will diminish as N Rx grows larger, further decreasing the Q factor. Figure 9 shows that S Rx remains fairly constant throughout the entire load resistance range. An explanation for this could be that the value S Rx attains simply makes the inter-turn capacitance, C turn , negligible for the frequency in question.
Furthermore, in order to estimate a suitable value for b in Eqs. 15, 14 is solved for b and values for cR 0 L and 2R Rx are obtained from Fig. 10 at the observed transition to the low-power region, at R 0 L ¼ 56 kX. By this procedure, a value of b ¼ 0:24 is obtained. Using this value for b, in order to test the validity of the theory on how to estimate R L,cutoff , values for cR 0 L and 2R Rx are taken from Fig. 10 at R 0 L ¼ 1 MX and inserted into Eq.15. The result is R L,cutoff ¼ 51 kX-reasonably close to the observed cutoff point at R L,cutoff ¼ 56 kX.

Measurements
In this section we present measurements used to confirm the validity of the simulations presented in the previous section.

MOSFET diode characterisation
In order to accurately estimate the power transfer efficiency, g, of the system described in Sect. 2, the MOSFET  . 10 Magnitude of the impedance terms in the denominator of Eq. 10 for the Rx coil optimised at different average equivalent load resistances Fig. 11 Power transfer efficiency, g, transmitted power, P S , and consumed power, P L , for coils optimised for different equivalent average load resistances. P S is the power delivered to the transmitting coil required in order to maintain an rms voltage of 1 V over the load, while P L is the power consumed at the load

Power transfer efficiency characterisation for varying load resistance
An experimental set-up was arranged according to Fig. 3 with a matched PCB coil driven by a power amplifier. An IC containing an on-chip coil, a shunt capacitor as matching network and a rectifier was manufactured in a 350 nm CMOS process and is modelled on the optimised design presented in our previous work, [6]. A microphotograph of the IC layout is presented in Fig. 13. This is a 5turn coil with a trace width of 35 lm, a trace separation of 6.0 lm and an outer diameter of 2.0 mm. Although that design turned out to be sub-optimal due to a previous error in the simulation model as detailed in Sect. 4, we use that design in this work in order to verify our now corrected simulation model. In addition to coil, matching network and rectifier, the IC also hosts temperature sensors which are not relevant to this work, but included to utilise leftover silicon area that was not needed in this work. The IC was glued to a PCB mounted at 10 mm from the Tx PCB as shown in the picture of Fig. 15. In order to emulate the situation in a monitoring system for power semiconductor modules where the sensors would be mounted some distance above a ground plane, the Rx PCB included a buried ground plane at a depth of 1.6 mm. This plane was also included in all simulations presented in this paper. To reduce the amount of induced current at sensitive nodes, the length of bond wires were kept to a minimum and the circuit goes directly down through vias at the bond wire pads to the bottom layer of the PCB, where the load resistor, R L , and voltage follower were placed as closely as possible to the vias.
The diode characterisation described in the previous subsection was used to estimate the power transfer efficiency, g ¼ P L =P S based on observed voltages, V L , at R L for different values of load resistance. For each load resistance point, the power was increased until a V L of 300 mV was obtained. The load resistances used ranged from 560 X to 100 kX. Due to the excessive power requirements, it was not possible to drive the PCB coil at lower resistances without overheating it. Therefore the power transfer efficiency characterisation was repeated for a two-turn, wire-wound air coil used as Tx coil and placed directly around the Rx chip as shown in the picture of in Fig. 16. Because of the closer proximity and higher Q factor of the wire coil, a higher efficiency was achieved  and it was possible to perform the measurements for load resistances down to R 0 L ¼ 56X. Because of the weak coupling between Tx and Rx coils, as is also the case for the PCB coil variant of this set-up, the resistance at the Rx side is insignificant for the Tx coil. Therefore, the power transfer efficiencies for the two cases (PCB coil and wire coil) should differ by a constant factor over the full resistance range. For the performed measurements, this factor was estimated to approximately 6 dB. Fig. 17 shows a plot of the power transfer efficiency from both types of measurement as a function of load resistance along with circuit simulations based on coil parameters given by electromagnetic simulations. These simulations use the same layer structure and material properties as the simulations presented in Sect. 4, except that air was used in place of the silicone gel. The power transfer efficiency for the wire coil has been shifted downwards by 6 dB and thus shows the expected behaviour of the PCB coil to be seen had measurements been done for lower load resistances.
Comparing the measurements with simulated values, Fig. 17 shows close agreement in general behaviour of the two graphs. However, the measured values differ by an approximately constant value between 5 and 12 dB. This discrepancy can have several explanations: One possible explanation could be that because the Tx coil is of very low impedance, the ESR of the matching components may be significant because they are comparable in size to the coil impedance. ESR values of R L,m ¼ 53 mX and R C,m ¼ 35 mX for the matching shunt inductor, L m,Tx , and series capacitor, C m,Tx , respectively, were obtained from data sheets. These are comparable to the ESR of the Tx coil of R Tx ¼ 573 mX and are thus likely significant, but circuit simulations show that they are unlikely to be the full explanation for the discrepancy in power transfer efficiency.
Another possibility could be that the DC characterisation of the MOSFET diode is not valid for the high-frequency case. However, no unexpected power consumption in the diode is visible in circuit simulations. It is however possible that the simulator omits effects such as those from the parasitic body diode which would exhibit a significant turn-off time due to the reverse-recovery effect [20] than a pure MOSFET diode and thus result in an increased reverse-leakage current during the negative half-cycles of the transmitted signal. To examine whether this was the case, the coils were immersed in liquid nitrogen in order to cool them down to -196 C. Because the reverse-recovery time in p-n junctions is proportional to absolute temperature [20], if p-n junction leakage is in fact a problem, it should be heavily mitigated by the lower temperature. However, the power transfer efficiency increased by merely 5 dB for the nitrogen-cooled coils, which is less than what is expected due to decreased resistance in the copper traces of the coils at the reduced temperature, which amounts to approximately 7 dB. Thus, the possibility of parasitic body diode turn-on being the main contributing factor is ruled out. Another characterisation of the MOS-FET diode was performed with the diode immersed in liquid nitrogen in order to take into account changes is forward voltage, V D , of the diode in the calculations.
Another source of error could be that bond wires reaching over the IC coil in order to connect the rectified voltage, V L , to the load resistor, R L , could reduce the power transfer efficiency because some energy transmitted by the PCB coil is absorbed by the bond wire loop instead of the IC coil. However, because of the weak coupling between the PCB and IC coils-the latter which is located very near the bond wires whose coupling with the PCB coil should therefore also be weak-this effect should be small.  However, it is expected that the coupling between the IC coil and the bond wires is stronger and thus that the bond wires, loaded by, R L could consume some of the stored magnetic energy in the IC coil, reducing it's Q factor, as well as affecting the rectifier's ability to rectify the induced voltage by superimposing a voltage, v l ðtÞ, on V L . v l ðtÞ will arrive in phase with the induced voltage, v emf ðtÞ, and will thus make it harder for the rectifier to rectify v emf ðtÞ.
The bond wire loop is estimated to occupy around 2.5% of the IC coil area, resulting in a voltage conversion factor of 0:025k Rx--BW , where k Rx--BW is the coupling coefficient between the IC coil and the bond wire loop. Although k Rx--BW is expected to be somewhat stronger than the coupling between the two coils, it is still expected to be small. Thus, it is likely that this phenomenon has only a minor effect on the power transfer efficiency.
It is also possible that the accuracy of the electromagnetic model is responsible for the discrepancy. The dielectric materials in the model are modelled as infinite layers in order to speed up the simulations. Had a full 3-dimensional (3D) model been used, it is possible that the accuracy could have been increased.
Furthermore, the manufacturing tolerances for the thicknesses of the layers in the manufactured IC are large, thus it is possible that parasitic elements such as e.g. substrate capacitance are more prominent than the simulation model shows.
In conclusion, we have identified some possible sources of errors in an attempt to explain the discrepancy between simulation models and measurement results. While it is difficult to say exactly which sources are most significant it is likely that the discrepancy does not have a single cause, but is rather a combination of multiple sources of error. However, we note again that the graphs exhibit a good matching in overall shape.

Conclusion
We have shown theoretically that for the low-power operation of on-chip coils with shunt capacitors as matching networks, there is a limit for where it is inefficient to further decrease the load in an attempt to reduce the transmitted power, and that beyond this limit the optimal coil geometry no longer depends on the load resistance. For the 350 nm CMOS process used in this paper, this limit appears to lie around 56 kX. This means that IC sensor systems powered by on-chip coils manufactured in this process technology, requiring a 1 V supply voltage and measuring 2 Â 2 mm 2 would not benefit of decreasing the power budget below about 20lW. Simulations show that such a power budget can be achieved at a transmitter power, P S , of 20 dBm. If the discrepancy between simulated and measured results is accounted for, P S amounts to 32 dBm (1.6 W), which is reasonable for a PCB coil. These values correspond to a power transfer efficiency of À39 dB, as seen in Fig. 8 at R 0 L ¼ 56 kX. We argue that a power budget in the 20 lW range is reasonable for our application-a temperature monitoring system for power semiconductor modules. As an example, using the temperature sensor presented in [21]-which consumes 14 lW at its highest operating temperaturewould leave at least 6 lW for other on-chip systems such as rectifier, analogue-to-digital converter (ADC) and load modulator.
Acknowledgements The work presented in this paper was funded by Svenska Kraftnät.
Funding Open access funding provided by Luleå University of Technology.
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Data Availibility Statement
The data generated during this study are available from the corresponding author on reasonable request.