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A 0.25–1.0 V fully synthesizable three-stage dynamic voltage comparator based XOR&XNOR&NAND&NOR logic

  • Mixed Signal Letter
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Abstract

To improve the performance of all-digital synthesizable comparators for the stochastic circuit, we present a three-stage rail-to-rail fully synthesizable dynamic voltage comparator. Compared with the state-of-the-art designs, the proposed comparator uses XOR, XNOR, NAND, and NOR logic gates to further improve the comparator’s common-mode input range, offset, speed and power-delay product (PDP). The comparator is implemented on CMOS 45 nm technology, operating with a supply voltage of 250 mV–1.0 V. The comparator has reduced the delay by 0.70 to \(0.82\times \), increased the standard deviation of offset by 1.28 to \(1.65\times \) and reduced the PDP down to \(0.67\times \) compared to NAND & NOR-based comparator. Hence, these improvements help to increase the performance of the stochastic Flash ADC, and improve the reliability of the stochastic PUF circuit.

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Acknowledgements

This research is supported in part by the National Key Research and Development Program of China under Grant No. 2019YFB2204500 and in part by the National Science Foundation of China under Grant No. 61874171 and in part by in part by the Science, Technology and Innovation Action Plan of Shanghai Municipality, China under Grant No. 1914220370.

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Authors and Affiliations

  1. Department of Micro-Nano Electronics and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University, Shanghai, 200240, China

    Ting Zhou, Xiaocui Li, Yuxin Ji & Yongfu Li

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  1. Ting Zhou
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  2. Xiaocui Li
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  3. Yuxin Ji
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  4. Yongfu Li
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Correspondence to Yongfu Li.

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Zhou, T., Li, X., Ji, Y. et al. A 0.25–1.0 V fully synthesizable three-stage dynamic voltage comparator based XOR&XNOR&NAND&NOR logic. Analog Integr Circ Sig Process 108, 221–228 (2021). https://doi.org/10.1007/s10470-021-01838-7

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